I put these conditions in different always and if-else-if statements, will design compiler & ISE be smart enough to recognise them and reduce hardware cost accordingly?
I had a tendency to write the conditions with a wire & assign statement e.g.: wire cond1; assign cond1 = pop && (process == 8'h25) || kick; but if synthesizers handles these, then it will save me some thinking.
always @ (posedge clk) begin if (pop && (process == 8'h25) || kick) whatever
There's an option in many synthesizers called "resource sharing" that will optimize for space if logic like these are found, but I think the default is to treat them as seperate blocks. Why bother with optimizations like this? IMO these should be the least to worry about.
Do save yourself some thinking like this, let the synthesis tools worry about optimization.
In general, I don't think that a synthesis tool will share resources between always blocks.
I find it best to "help" the synthesys tool where possible.
I would re-write the above code (verilog is a bit rusty)
parameter FinalCount := 8'h25 ; wire AtFinalCount
Hi Frank,
The tests that you wrote will create what is called "common sub-expressions". These are typically eliminated very early in the flow through synthesis.
So, I am convinced that you are free to write the same tests in different processes, and it should not affect the synthesis result.
Just try to keep them the same as much as possible, so that common subexpression elimination is guaranteed to work.
Rob
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