Field-Programmable Gate Arrays

don't care condition

Hi, Please let me know - what is the advantage of fully specifying don't care conditions? -Sandi

2 comments posted 20yrs

posted by sandipon.basu

2 comments posted 20yrs posted by sandipon.basu

xilinx linux source?

I have an evm on order, but is there a place I can download the PPC linux for Virtex-4? I want to make sure I can build...

8 comments posted 20yrs

posted by someone

8 comments posted 20yrs posted by someone

Spartan3 pullups

Hi, We have several products that use S3's, with a number of fpga pins connected to dipswitches. The dips switch to gro...

7 comments posted 20yrs

posted by jjlarkin

7 comments posted 20yrs posted by jjlarkin

microblaze GNU tools for win32 binaries (from 8.1 build) for download

Hi I have compiled the GNU tools for microblaze (from the 8.1 source from Xilinx website) the win32 binaries are downlo...

1 comments posted 20yrs

posted by antti

1 comments posted 20yrs posted by antti

Strange problem with sysace + linux + Ace on SanDisk.

After upgrade ace file and some software code from application in linux, we seen some compact flash booting up 15 secon...

0 comments posted 20yrs

posted by tony.p.lee

0 comments posted 20yrs posted by tony.p.lee

ISE 8.1.01i does not implement new BUS macro

hi I am trying to implement new bus macro "busmacro_xc2vp_l2r_async_na rrow.nmc" in ISE 8.1.01i, while following error...

0 comments posted 20yrs

posted by pasacco

0 comments posted 20yrs posted by pasacco

Maximum system frequency on FPGA/CPLD

Hi There. Xilinx CPLD XCR3384XL with speed grade -7 have (according to the datasheet) a maximum clock frequency at 135M...

3 comments posted 20yrs

posted by raybakk

3 comments posted 20yrs posted by raybakk

BPSK modulation on Xilinx FPGA

Hi everybody, I'm trying to implement a BPSK modulation. A sin waveform has to be generated at a given frequency (1MHz)...

11 comments posted 20yrs

posted by Ben.Marpe

11 comments posted 20yrs posted by Ben.Marpe

LDPC

Hi "LDPC" is a common platform on LDPC codes for sharing ideas, research problems, issue discussions, software and neat...

0 comments posted 20yrs

posted by saad.qaisar

0 comments posted 20yrs posted by saad.qaisar

Quartus Fitter Warning

Hi everybody, I get this warning under Quartus 5.1 : "Performance of this circuit may degrade because the Fitter Delay...

1 comments posted 20yrs

posted by patrick.melet

1 comments posted 20yrs posted by patrick.melet

Gbit technology selection?

I've got an app where I need to communicate between several cards in a chassis, with cable lengths up to about 15cm, an...

0 comments posted 20yrs

posted by abuse

0 comments posted 20yrs posted by abuse

Die Area

Hi Guys I'm looking for some die area information on FPGAs. It is prooving quite difficult to find any information so if...

19 comments posted 20yrs

posted by noelhurley

19 comments posted 20yrs posted by noelhurley

For our Study We need STM1, 4 , 16 Block diagram where to get it

Dears I am serching the web for te block diagram of STM 1, 4 &16 Block diagram with the component information on board...

4 comments posted 20yrs

posted by satishkmys

4 comments posted 20yrs posted by satishkmys

Parallel Cable IV does not work with parallel to usb cable

Hallo, I bought recently a notebook with only usb, firewire, ethernet and 1 pcmcia connectors. I use Parallel Cable IV....

12 comments posted 20yrs

posted by marc

12 comments posted 20yrs posted by marc

Ethernet : MAC vs PHY

I have a 10BASE-T MAC/stack design (using PicoBlaze, BTW) which I'm trying to bring up on the Avnet/Memec S3MB Spartan3...

2 comments posted 20yrs

posted by twv

2 comments posted 20yrs posted by twv