I 'm also trying to use a master ip on the PLB bus and I also use the IPIF interface from the "Create Peripheral" wizard in EDK's XPS. Like you I have some troubels with writhing and reading (I want to write and read to/from a BRAM on the PLB-Bus) You say that the slave attachment is also used for the master trasaction. When I look at the timing diagram on pg 116 of the plb_ipif.pdf
it say that when you read you will get a Bus2IP_WrReq is this correct, because you want to read and not write. Is this correct?
I have made a small FSM to test a single read and write (at the bottom of the message is my VHDL-code)
I have a state (PrepareWr_State and PrepareRd_State) to make sure all the addresses are correct I have a state (ReqWr_State and ReqRd_State) for the request =>
IP2Bus_MstWrReq and IP2Bus_MstRdReq I have a state (AckWr_State and AckRd_State) for the ack that the IPIF can read/write from/to my ip => IP2Bus_WrAck and IP2Bus_RdAck I have a state (OkWr_State and OkRd_State) so I know everything went well
But there must be something wrong because it doesn't work, when I want to write something, my FSM stays in the ReqWr_State, and when I want to read something it also doesn't do what it should do (or atleast what I think it should do)
Can you help me please?
STATE_TRANSITION_LOGIC: process (ACTUAL_STATE, pushR, pushL, pushU, pushD, Bus2IP_MstLastAck, Bus2IP_WrReq, Bus2IP_RdReq) variable counter_Rd : integer range 0 to 15; variable counter_Wr : integer range 0 to 15; begin
case ACTUAL_STATE is when idle =>
if (pushR = '0') then -- pushR is active low NEXT_STATE