Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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adding FPGA grounds
One of my guys is suggesting that we ground unused balls on an FPGA and compile them to be low outputs, the idea being to reduce ground impedance and add some damping. Has anyone done this? Does it...
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2 years ago
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Real Time Simulation
I'm working on a project with a number of non-EE, non-CE types. A CE mocke d up a real time simulation of the UI which will be done in the FPGA. I am writing the HDL which everyone is nervous about...
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2 years ago
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What is wrong with low level code?
I recently posted a Verilog module to this forum, and someone responded tha t I was coding at a very low level, which was true; I was referring to XOR gates, NAND gates, NOR gates, and NOT gates. Is...
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2 years ago
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Piplineing logic alot? I have a tool for you
Try out the PipelineC compiler - it pipelines combinatorial logic for you. It is also a full hardware description language - thats cool. Looking for folks interested in using or contributing to the...
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2 years ago
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FPGA sensitivities
I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs some voltages: 1.8 aux no measurable DC effect 3.3 vccio no...
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2 years ago
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Active HDL Entity Retention
I have multiple entities in a file. I renamed one of them. The design bro wser now shows both the old entity and the new one. It won't allow me to d o anything with the old entity like delete it. The...
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2 years ago
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Multi-FPGA Interconnection: latest techniques
Hi Experts, In FPGA Prototyping/Emulation flows, Multi-FPGA partitioning puts limitation on performance due to limited IO pins. What are the latest Multi-FPGA Interconnection techniques available...
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2 years ago
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Is there any way to get a different font for code sections?
When I make posts to this forum and have code to show, I do something like this: [code] module xyz (); // ... endmodule [/code] This has worked on other forums, creating a window with the text in a...
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2 years ago
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How powerful is Verilog at using parameters to specify designs?
I have a design in mind that would fit in this skeleton: [code] module xyz ( result, leftOp, rightOp); parameter integer nmBits = 1; localparam integer highBit = nmBits - 1; output result; input [...
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2 years ago
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Exponential Regression by XSG
I want to perform an exponential regression function by using the Xilinx system generator. To support fixed-point data, 12 bit, and 1 MSPS. That to estimate a logarithmic increase and decrease the...
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2 years ago
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exponential regression in XSG
Hi Guys, I hope everybody is fine. I would like to perform an exponential regression function by using the Xilinx system generator. could you please make help me. thanks and regards M. I. Ibrahim
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2 years ago
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Is it illegal to use an (enum) as a Verilog function input?
I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean value as input, but while I was wa iting for input on that I decided to rewrite a...
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2 years ago
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Can anyone explain "cannot currently create a parameter of type" compilation error message?
I've written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit, which returns a logical one in (result) if (left) has the same value as (right),...
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2 years ago
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Can a Verilog function take a boolean argument?
I've got a Verilog function that I'd like to behave slightly differently depending on the value of a boolean argument, an argument whose value can be either (true) or (false). I tried: [code] module...
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2 years ago
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Non-binary NCO Modulus
I recall digging deeply into NCO design some years ago. I am trying to rem ember the dirty details of what I had learned. In particular I have a non- binary modulus. I'd like to find the simplest way...
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2 years ago
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