Field-Programmable Gate Arrays

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A bewildering Visio-2019 problem!

Unfortunately, I met a bewildering problem with Visio-2019. I have been using Visio-2019 to make circuit drawings, ever...
1 comments posted 5yrs
posted by wtxwtx
1 comments posted 5yrs posted by wtxwtx

MachXO2 pin mismatch error

Hi, I am trying to use a PMI ROM memory block in Lattice Diamond/VHDL: decoder_rom0 : pmi_rom generic map ( pmi_addr_wi...
1 comments posted 5yrs
posted by peter.pan
1 comments posted 5yrs posted by peter.pan

Fully Comitted to LVDS as Comparitors

I working on a design where there will be some five sigma-delta ADCs and several specific level detect inputs each usin...
0 comments posted 5yrs
posted by gnuarm.deletethisbit
0 comments posted 5yrs posted by gnuarm.deletethisbit

Achronix?

Has anyone used Achronix FPGAs?
2 comments posted 5yrs
posted by jlarkin
2 comments posted 5yrs posted by jlarkin

Communist Chinese Military Companies

A new FPGA company in China has appeared on a list of Communist Chinese Mil itary Companies (CCMCs). One article I read...
0 comments posted 5yrs
posted by gnuarm.deletethisbit
0 comments posted 5yrs posted by gnuarm.deletethisbit

Division Algorithms

I am looking for an algorithm to calculate a floating point divide. There a re a number of options, but the one that is...
2 comments posted 5yrs
posted by gnuarm.deletethisbit
2 comments posted 5yrs posted by gnuarm.deletethisbit

Achronix Semiconductor in Talks for Merger

An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be s...
24 comments posted 5yrs
posted by gnuarm.deletethisbit
24 comments posted 5yrs posted by gnuarm.deletethisbit

Fixed Point Arithmetic

I don't know why I thought it would be easy. The arithmetic is not so hard by itself. But changing all the equations to...
9 comments posted 5yrs
posted by gnuarm.deletethisbit
9 comments posted 5yrs posted by gnuarm.deletethisbit

PHB FPGA question

OK, pointy-haired boss question. Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock from an LVDS input....
3 comments posted 5yrs
posted by jlarkin
3 comments posted 5yrs posted by jlarkin

Temperature Sensor Error

Hi everyone, I'm trying to implement the following code on the NEXYS A7 board and it seems the I2C communication isn't...
6 comments posted 5yrs
posted by bk201n
6 comments posted 5yrs posted by bk201n

CRC is an FPGA PITA

I had a newbie working on a bit wise CRC32 implementation and he could not get the results of any of the many online CR...
18 comments posted 5yrs
posted by gnuarm.deletethisbit
18 comments posted 5yrs posted by gnuarm.deletethisbit

Gowin - This Just Got Real

I've been watching the various FPGA startup companies and a couple have pro duct available through mainstream distribut...
5 comments posted 5yrs
posted by gnuarm.deletethisbit
5 comments posted 5yrs posted by gnuarm.deletethisbit