Field-Programmable Gate Arrays

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Synthesizable open FPGA cores

Hi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluatin...
1 comments posted 5yrs
posted by gparthu
1 comments posted 5yrs posted by gparthu

To Reset or not to Reset, That is the Question!

Whether tis nobler to suffer the slings and arrows of outrageous judgement or just add the pointless, incorrectly worki...
4 comments posted 5yrs
posted by gnuarm.deletethisbit
4 comments posted 5yrs posted by gnuarm.deletethisbit

Using DSP Units

I working with the Gowin GW1N devices and need to do some serious math. By serious, I mean a number of calculations, no...
7 comments posted 5yrs
posted by gnuarm.deletethisbit
7 comments posted 5yrs posted by gnuarm.deletethisbit

Finally! I figgured it out accidentally.

Sometimes the tools are hard to figure out. I've been looking for a way to leave my source files in MY source directory...
2 comments posted 5yrs
posted by gnuarm.deletethisbit
2 comments posted 5yrs posted by gnuarm.deletethisbit

HP "owning" the software for Xilinx-FTDI drivers???

Someone new on the project is talking about how HP owns the driver code for the FTDI JTAG chip used to program Xilinx p...
6 comments posted 5yrs
posted by gnuarm.deletethisbit
6 comments posted 5yrs posted by gnuarm.deletethisbit

Active-HDL Throws Error

My code is assigning an incremented unsigned value to an aggregate so the s um and carry can be extracted without dupli...
14 comments posted 5yrs
posted by gnuarm.deletethisbit
14 comments posted 5yrs posted by gnuarm.deletethisbit

Gowin Synthesis Software

Just had my first taste of the company supplied software from Gowin Semicon ductor. It's ok. Documentation is terrible...
0 comments posted 5yrs
posted by gnuarm.deletethisbit
0 comments posted 5yrs posted by gnuarm.deletethisbit

XLNX on the Auction Block?

I'm reading reports that AMD is working on buying Xilinx and Qualcom and Broadcom may make bids as well. Stock is up fr...
0 comments posted 5yrs
posted by gnuarm.deletethisbit
0 comments posted 5yrs posted by gnuarm.deletethisbit

adding FPGA grounds

One of my guys is suggesting that we ground unused balls on an FPGA and compile them to be low outputs, the idea being...
20 comments posted 5yrs
posted by jlarkin
20 comments posted 5yrs posted by jlarkin

Real Time Simulation

I'm working on a project with a number of non-EE, non-CE types. A CE mocke d up a real time simulation of the UI which...
4 comments posted 5yrs
posted by gnuarm.deletethisbit
4 comments posted 5yrs posted by gnuarm.deletethisbit

What is wrong with low level code?

I recently posted a Verilog module to this forum, and someone responded tha t I was coding at a very low level, which w...
14 comments posted 5yrs
posted by kvnsmnsn
14 comments posted 5yrs posted by kvnsmnsn

Piplineing logic alot? I have a tool for you

Try out the PipelineC compiler - it pipelines combinatorial logic for you. https://github.com/JulianKemmerer/PipelineC/...
0 comments posted 5yrs
posted by absurdfatalism
0 comments posted 5yrs posted by absurdfatalism