My code is assigning an incremented unsigned value to an aggregate so the s um and carry can be extracted without duplicating logic or excessive lines of code (VHDL can be verbose we all know). But it seems this one usage mak es the Active-HDL simulator complain. I'm adding an integer 1 to the unsig ned counter value after being resized to be 1 bit larger to match the left hand side aggregate. I'll post the code below.
It seems the combination of using the left hand aggregate, resized unsigned and the addition/subtraction of an integer is what causes a problem. I wo uld report this to Aldec, but I'm pretty sure they don't have a way to repo rt bugs if you are not a customer with a current maintenance contract.
-- Test synthesis of counters and carry out flags library ieee; use ieee.NUMERIC_STD.all; use ieee.std_logic_1164.all;
-- use work.Common.all;
entity VHDL_test is generic( CLK_HZ : REAL := 33.554432E6 ); port( -- Clk : in std_logic := '1'; Cnt_En : in std_logic := '1'; Test_Out_a : out std_logic; Carry_Out_a : out std_logic ); end VHDL_test;
architecture TB_ARCH of VHDL_test is constant Clock_Half_Period : time := 500 ms / CLK_HZ; -- 14901 ps; constant Cntr_Width : positive := 8; constant Cntr_Modulus : positive := 2**Cntr_Width; constant One_slv : unsigned(Cntr_Width downto 0) := "000000001"; signal Clk : std_logic := '1'; signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (other s => '0'); begin
Clk_gen: Clk