Active-HDL Throws Error

My code is assigning an incremented unsigned value to an aggregate so the s
um and carry can be extracted without duplicating logic or excessive lines
of code (VHDL can be verbose we all know). But it seems this one usage mak
es the Active-HDL simulator complain. I'm adding an integer 1 to the unsig
ned counter value after being resized to be 1 bit larger to match the left
hand side aggregate. I'll post the code below.
It seems the combination of using the left hand aggregate, resized unsigned
and the addition/subtraction of an integer is what causes a problem. I wo
uld report this to Aldec, but I'm pretty sure they don't have a way to repo
rt bugs if you are not a customer with a current maintenance contract.
-- Test synthesis of counters and carry out flags
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- use work.Common.all;
entity VHDL_test is
generic(
CLK_HZ : REAL := 33.554432E6 );
port(
-- Clk : in std_logic := '1';
Cnt_En : in std_logic := '1';
Test_Out_a : out std_logic;
Carry_Out_a : out std_logic
);
end VHDL_test;
architecture TB_ARCH of VHDL_test is
constant Clock_Half_Period : time := 500 ms / CLK_HZ; -- 14901 ps;
constant Cntr_Width : positive := 8;
constant Cntr_Modulus : positive := 2**Cntr_Width;
constant One_slv : unsigned(Cntr_Width downto 0) := "000000001";
signal Clk : std_logic := '1';
signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (other
s => '0');
begin
Clk_gen: Clk
Reply to
Rick C
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sum and carry can be extracted without duplicating logic or excessive line s of code (VHDL can be verbose we all know). But it seems this one usage m akes the Active-HDL simulator complain. I'm adding an integer 1 to the uns igned counter value after being resized to be 1 bit larger to match the lef t hand side aggregate. I'll post the code below.
ed and the addition/subtraction of an integer is what causes a problem. I would report this to Aldec, but I'm pretty sure they don't have a way to re port bugs if you are not a customer with a current maintenance contract.
ers => '0'); > begin > > Clk_gen: Clk > -- (Carry_Out_a, nxt_cnt_a)
Reply to
Rick C
On Monday, October 19, 2020 at 10:39:28 PM UTC-6, snipped-for-privacy@gmail.com w rote:
he sum and carry can be extracted without duplicating logic or excessive li nes of code (VHDL can be verbose we all know). But it seems this one usage makes the Active-HDL simulator complain. I'm adding an integer 1 to the uns igned counter value after being resized to be 1 bit larger to match the lef t hand side aggregate. I'll post the code below.
gned and the addition/subtraction of an integer is what causes a problem. I would report this to Aldec, but I'm pretty sure they don't have a way to r eport bugs if you are not a customer with a current maintenance contract.
ers => '0'); > > begin > > > > Clk_gen: Clk > > > -- (Carry_Out_a, nxt_cnt_a)
Reply to
Kevin Neilson
I don't think that is the case.
I know that in the past XST used to allow illegal VHDL constructs which resulted in Leonardo Spectrum adding a special "XST" switch to stop users complaining but there is no advantage in Aldec having a doggy parser. Also most EDA vendors use the same commercial parsers from Verific.
The problem is that most free/student versions are older releases (Mentor does the same, OEM=2019.1, latest=2020.3). So I wouldn't be surprised if this bug has already been fixed in the latest release (I am sure somebody with a commercial license can confirm this).
Aldec is pretty good when it comes to VHDL support.
Logging this bug however will not help Rick as it will probably take a year for the bug to be fixed and for the free version to get the update. So I would use the simple concatenation syntax which I actually find much easier to read, as they say "KISS",
Hans
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HT-Lab
rovided the "free" software). Neither one has a means of reporting bugs unl ess you have an active maintenance account. I've sent both an email. Don't know if they will ever get back to me or accept my report of the bug.
log tool out. They were paying a bounty for bug reports. I think they let y ou use the software for free to find bugs and if you found 10 you got a lif etime subscription to the tool. Not sure what you got for lesser quantities .
its lowest form.
c.
I would point out that this is not a compiler error, but a run time error. I think that is significantly different, i.e. not exactly a parser error m ost likely.
I've already gone with the simpler and shorter right hand side
(Carry_Out_a, nxt_cnt_a)
Reply to
Rick C
Actually I downloaded what Intel provides for free today and it's Modelsim 2020.2. But it seems to me that for a long time it was a few Modelsim 10.x, a few years old at least.
Rick's example seems to work with that Modelsim, in ghdl too although ghdl doesn't claim full VHDL 2008 compatibility.
Don't have an Aldec license unfortunately.
Reply to
Anssi Saari
It isn't any different - I have a fully paid up in-maintenance Aldec HDL license.
A different thing: I moved the line you quote above out of the process this afternoon and the simulator choked with a clash between Gowin's PLL behavioural and something - ran out of delta time iterations at 0ps !
I haven't sorted it out yet - came home for tea instead.
MK
Reply to
Michael Kellett
Someone else reported that ghdl did not work. But that seems to be an issue with ghdl not supporting all the useful features of VHDL-2008.
ghdl -a --std=08 VHDL_test.vhVHDL_test.vhd:26:17:error: can't match 'nxt_cnt_a' with type std_ulogic VHDL_test.vhd:26:17:error: target is not a signal name
Maybe your version of ghdl has additional features implemented.
Maybe I'll try the Intel tools. I'm used to Active-HDL, but there's not so much difference.
--
  Rick C. 

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Reply to
Rick C
provided the "free" software). Neither one has a means of reporting bugs u nless you have an active maintenance account. I've sent both an email. Don' t know if they will ever get back to me or accept my report of the bug.
rilog tool out. They were paying a bounty for bug reports. I think they let you use the software for free to find bugs and if you found 10 you got a l ifetime subscription to the tool. Not sure what you got for lesser quantiti es.
to its lowest form.
h
ific.
e
am
or. I think that is significantly different, i.e. not exactly a parser err or most likely.
e.
ft hand aggregate works. Replacing the RESIZE as above makes it work. Cha nging the integer literal with an unsigned constant makes it work. In fact , my constant definition can likely be replaced with a "1" and retain the R ESIZE, but that's so much more typing than above.
me down saying I need to contact Lattice. The way they worded it, I think Lattice might be paying them a set price with no updates without paying a l ump sum again. They said, "For the ActiveHDL in the Lattice tools you have to contact Lattice. Although we provide Lattice with the simulator, we don 't have access to it once it is in their tools suite." That's a strange wa y to put it, "don't have access".
guard dogs.
imulator.
Not sure which line you are referring to. The line with the error is a con current statement and not in a process. Here are the three cases I've test ed so far.
(Carry_Out_a, nxt_cnt_a)
Reply to
Rick C
Maybe, it's the latest release version 0.37 from last February so not exactly new.
Reply to
Anssi Saari
That guy reported updating ghdl and the aggregate then working ok. Thanks for your info.
--
  Rick C. 

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Reply to
Rick C
I agree, but I was replying to Kevin's post where he mentioned not parsing legal code,
Hans
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Reply to
HT-Lab
Thanks, that is good news and I should have checked this before posting. I am on Quartus 18.1 and assumed Modelsim would still be on the 2019 series.
GHDL is an amazing piece of software and kudos to the developers. It is a shame they picked ADA as more young programmers (i.e. student with lots of spare time) are familiar with Python, C, Julia?, Go? ... I lost track, still impressive free software,
Hans
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HT-Lab
e
I thought I might give ghdl a try, but I'm not clear on how to run it. Th ey don't have an idiot's guide so I'm sure I totally messing it up. To sta rt with I copied the folder ghdl from the zip file ghdl-0.37-mingw64-llvm.z ip to C:\Program Files Then in the bin subdir I see two exe files, ghdl1-l lvm.exe and ghdl.exe. Which is used?
Then I tried running by clicking on them, but I suspect that produces a com mand line window that immediately goes away because I didn't have any comma nd line parameters. I don't see any sign of the window though, just a mous e cursor blink and the Windows Explorer window blinks. I get this same beh avior with a UI simulation executable. I tried turning off the AVS but to no avail.
I take it I need to put together a batch file to run ghdl?
It seems like it would be a good idea to use a vendor independent simulator , but I'm not big on steep learning curves.
--
  Rick C. 

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Reply to
Rick C
Yes, this is the command sequence I used a few years ago for one my designs:
ghdl -a --ieee=synopsys -fexplicit dut.vhd ghdl -a --ieee=synopsys -fexplicit testbench.vhd ghdl -e --ieee=synopsys -fexplicit testbench ./testbench.vhd --stop-time=200ms --ieee-asserts=disable --vcd=my.vcd
I was quite impressed it worked first time out of the box. However, I quickly went back to Modelsim as a good debugging environment is so important. This is probably the reason why I still don't like Vivado. It has most bells and whistles but I find it too cumbersome to use.
Good luck,
Hans
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HT-Lab

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