Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Intel ModelSim Starter Edition is available free now!
Hi, Intel ModelSim Starter Edition is available free now! 10,000 line code limit, VHDL-2002 version, running speed is very very slow, but it is enough for debugging grammars. It needs to take 3 hours...
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1 year ago
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How to increase data of std_logic_vector by 1 in VHDL-2002
Hi, It is a long time headache for me to increase a data of std_logic_vector by 1. Here are examples: LIBRARY ieee; USE use constant ONE : std_logic_vector(7 downto 0); signal Series_Number :...
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1 year ago
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How to start with FPGA as "coprocessor"
Hi, I have a certain interest in a mathematical puzzle that I have not been able to solve using a normal CPU, and I thought that using an FPGA could work. For this, I would like to assign some work...
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1 year ago
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VHDL2019 Webinars
In case you missed it Aldec (Jim Lewis) is doing a webinars series on VHDL2019. It looks like I missed the first one as it start with Part2, Regards, Hans.
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1 year ago
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A bewildering Visio-2019 problem!
Unfortunately, I met a bewildering problem with Visio-2019. I have been using Visio-2019 to make circuit drawings, everything goes well until yesterday. I modified a drawing, and generated a PDF file,...
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1 year ago
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Research Assistantship (Fall, 2021) at Dept. of Computer Engineering, Hallym University, Korea
Research Assistantship (Fall, 2021) at the Graduate School, Dept. of Comput er Engineering, Hallym University, Korea The of the Hallym University seek to recruit pr omising PhD and MSc or MSc-PhD...
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1 year ago
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Hi can anyone please tell me how to rectify this error
Hi can anyone please tell me how to rectify this error ERROR:MapLib:30 - LOC constraint J17 on topsegF is invalid: No such site on the device. To bypass this error set the environment variable...
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2 years ago
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MachXO2 pin mismatch error
Hi, I am trying to use a PMI ROM memory block in Lattice Diamond/VHDL: decoder_rom0 : pmi_rom generic map ( pmi_addr_width => 3, pmi_data_width => decoder_rom_data'length, pmi_regmode => "noreg",...
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2 years ago
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Fully Comitted to LVDS as Comparitors
I working on a design where there will be some five sigma-delta ADCs and several specific level detect inputs each using an LVDS input pair as a comparator. So I'm pretty committed to this working....
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2 years ago
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Achronix?
Has anyone used Achronix FPGAs?
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2 years ago
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Communist Chinese Military Companies
A new FPGA company in China has appeared on a list of Communist Chinese Mil itary Companies (CCMCs). One article I read says this does not mean they ar e on the US military end user list (MEU) or the...
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2 years ago
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Division Algorithms
I am looking for an algorithm to calculate a floating point divide. There a re a number of options, but the one that is most clear to me and easiest to implement on the hardware I am designing seems...
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2 years ago
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Achronix Semiconductor in Talks for Merger
An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors. Achronix has been profitable, so this should be a good deal....
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2 years ago
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Fixed Point Arithmetic
I don't know why I thought it would be easy. The arithmetic is not so hard by itself. But changing all the equations to normalize the variables is n ot so easy. Then there is the issue of needing to...
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2 years ago
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PHB FPGA question
OK, pointy-haired boss question. Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock from an LVDS input. We have a resync flop in an i/o cell, clocked by this, with a D input from...
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2 years ago
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