Field-Programmable Gate Arrays

Calculation of throughput of sub-block in digital design (I)

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of...

0 comments posted 4yrs

posted by matrixofdynamism

0 comments posted 4yrs posted by matrixofdynamism

Old versions of quartus

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone k...

5 comments posted 4yrs

posted by chris

5 comments posted 4yrs posted by chris

VHDL project. Connecting components to one component

Hello guys, I am student at high school interested in VHDL programming and post quantum algorithms. I have a code where...

1 comments posted 4yrs

posted by durko208

1 comments posted 4yrs posted by durko208

BeMicro Cyclone III 64-bit drivers

I found my old BeMicro Cyclone III board laying around the other day and ha ppen to have a use for it - if I can get it...

2 comments posted 4yrs

posted by maurvir

2 comments posted 4yrs posted by maurvir

Is it possible to amplify weak lows and weak highs?

I am in possession of a book that says if the gate of an N-channel MOSFET i s low (say 0 volts), then the output is hig...

2 comments posted 4yrs

posted by kvnsmnsn

2 comments posted 4yrs posted by kvnsmnsn

How to Implement a Random Access Memory at the Transistor Level

I don't know if this is the right forum to post this to. If there's a forum that would be more appropriate for a questi...

2 comments posted 4yrs

posted by kvnsmnsn

2 comments posted 4yrs posted by kvnsmnsn

Verilog HDL Finite State Machine - detecting a decimal number

Hi all, I am trying to build a sequence detector to detect a decimal number like 10 92 when a stream of numbers from 0-...

1 comments posted 4yrs

posted by tanwartanishk5

1 comments posted 4yrs posted by tanwartanishk5

Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design

Hello, I have a Stratix 10 design that is based around an ip core generated using Intel's HLS. The core does some simpl...

6 comments posted 4yrs

posted by chris

6 comments posted 4yrs posted by chris

UDP -FPGA point to point

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol...

3 comments posted 4yrs

posted by manauroles

3 comments posted 4yrs posted by manauroles

Xilinx forums have disappeared?

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads t...

10 comments posted 4yrs

posted by wzab01

10 comments posted 4yrs posted by wzab01

Is there any software I can use to transform state machines in VHDL into drawings?

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL...

7 comments posted 4yrs

posted by wtxwtx

7 comments posted 4yrs posted by wtxwtx

GDB from my university...

CS302 ? Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counte...

2 comments posted 4yrs

posted by yousaftehseen007

2 comments posted 4yrs posted by yousaftehseen007

PLL dynamic phase shift

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png...

0 comments posted 5yrs

posted by feiphung

0 comments posted 5yrs posted by feiphung

A state machine design problem

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal Out...

1 comments posted 5yrs

posted by wtxwtx

1 comments posted 5yrs posted by wtxwtx

Synthesis : Pan's Algorithm

Have anyone studied Pan's Algorithm previously ? http://people.eecs.berkeley.edu/~alanmi/publications/2005/iwls05_smr.p...

0 comments posted 5yrs

posted by feiphung

0 comments posted 5yrs posted by feiphung