Latest threads in Field-Programmable Gate Arrays

Development tools for Xilinx Spartan 3

For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with...

4 4yrs

me

4 4yrs me

Calculation of throughput of sub-block in digital design (I)

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of...

0 4yrs

matrixofdynamism

0 4yrs matrixofdynamism

Old versions of quartus

Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone k...

5 4yrs

chris

5 4yrs chris

VHDL project. Connecting components to one component

Hello guys, I am student at high school interested in VHDL programming and post quantum algorithms. I have a code where...

1 4yrs

durko208

1 4yrs durko208

BeMicro Cyclone III 64-bit drivers

I found my old BeMicro Cyclone III board laying around the other day and ha ppen to have a use for it - if I can get it...

2 4yrs

maurvir

2 4yrs maurvir

Is it possible to amplify weak lows and weak highs?

I am in possession of a book that says if the gate of an N-channel MOSFET i s low (say 0 volts), then the output is hig...

2 4yrs

kvnsmnsn

2 4yrs kvnsmnsn

How to Implement a Random Access Memory at the Transistor Level

I don't know if this is the right forum to post this to. If there's a forum that would be more appropriate for a questi...

2 4yrs

kvnsmnsn

2 4yrs kvnsmnsn

Verilog HDL Finite State Machine - detecting a decimal number

Hi all, I am trying to build a sequence detector to detect a decimal number like 10 92 when a stream of numbers from 0-...

1 4yrs

tanwartanishk5

1 4yrs tanwartanishk5

Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design

Hello, I have a Stratix 10 design that is based around an ip core generated using Intel's HLS. The core does some simpl...

6 4yrs

chris

6 4yrs chris

UDP -FPGA point to point

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol...

3 4yrs

manauroles

3 4yrs manauroles

Xilinx forums have disappeared?

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads t...

10 4yrs

wzab01

10 4yrs wzab01

Is there any software I can use to transform state machines in VHDL into drawings?

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL...

7 5yrs

wtxwtx

7 5yrs wtxwtx

GDB from my university...

CS302 ? Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counte...

2 5yrs

yousaftehseen007

2 5yrs yousaftehseen007

PLL dynamic phase shift

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png...

0 5yrs

feiphung

0 5yrs feiphung

A state machine design problem

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal Out...

1 5yrs

wtxwtx

1 5yrs wtxwtx

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