Field-Programmable Gate Arrays

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Lattice FPGA

Hi I was hoping to get some opinions on Lattice FPGAs compared to Xilinx an Altera. I see they have a SC device out. How...
24 comments posted 20yrs
posted by maxascent
24 comments posted 20yrs posted by maxascent

Are Quad-processors advantageous?

I was considering purchasing an AMD64 quad-processor system, but have no idea whether any of the FPGA development tool...
7 comments posted 20yrs
posted by News5
7 comments posted 20yrs posted by News5

JTAG programing specs for XC18V01 PROM

Would anyone know where to get the JTAG programming specs (and programming times, page sizes, etc) for the XC18V01? I'd...
6 comments posted 20yrs
posted by ceb.dideas
6 comments posted 20yrs posted by ceb.dideas

FPGA

Free Manpower Recruitment Service for recent graduate FPGA Engineers http://www.fpgasps.com/
0 comments posted 20yrs
posted by manjunath.rg
0 comments posted 20yrs posted by manjunath.rg

need help on asynchronous buffer

Hi, I'm trying to do implement a buffer in Virtex II pro. My system has 8 bits 100 Mbps as an inputs and 16 bits 2.5Gbp...
8 comments posted 20yrs
posted by jdonjdon
8 comments posted 20yrs posted by jdonjdon

ISE usage help

Hi Gang ! I am using ISE 8.1sp2 and ISE 7.1sp4 (same challenge with both versions). I have an output bus, looks like th...
0 comments posted 20yrs
posted by russelmann
0 comments posted 20yrs posted by russelmann

need help with vhdl code in custom IP

Hi, I'm trying to do multiply-and-accumulate (MAC) in a custom IP created by Create/Import IP peripherals in XPS. Xilin...
0 comments posted 20yrs
posted by jamiehl
0 comments posted 20yrs posted by jamiehl

Smarter Power supplies arrive

It is good to the the venerable LM317, has some smarter offspring These new devices allow fine software control of Vcc,...
1 comments posted 20yrs
posted by no.spam
1 comments posted 20yrs posted by no.spam

need help on 16 bit risc processor code

hello guys can i get complte code for a 16 bit risc processor written in VHDL, i have developed code for it but im not...
0 comments posted 20yrs
posted by selva991
0 comments posted 20yrs posted by selva991

How to get eps file from XST RTL viewer for LATEX

Guru's I want to take the RTL schematic generated by XST to LATEX doc. Basically I need an .eps file. When I tried to c...
5 comments posted 20yrs
posted by santhosh_h_98
5 comments posted 20yrs posted by santhosh_h_98

BRAM for virtex-4

Hi all, i am using the following code for BRAMs and i copied these instantiations from virtex-4 libraray.But still i am...
2 comments posted 20yrs
posted by bachimanchi
2 comments posted 20yrs posted by bachimanchi

OpenSPARC released

For those who are interested, SUN released Open SPARC today: http://opensparc-t1.sunsource.net/download_hw.html Verilog...
61 comments posted 20yrs
posted by pablobleyer
61 comments posted 20yrs posted by pablobleyer

Virtex-4 RocketIO and G.709 OTU-2

Hi all, Did some company already implemented G.709 OTU-2 on Virtex-4 using the RocketIO? In other words: the maximum bi...
14 comments posted 20yrs
posted by taileb.mehdi
14 comments posted 20yrs posted by taileb.mehdi

Xilinx Square Root Unit

Hi guys, I was wondering if anyone here knows the technique that the Xilinx floating-point square-root core employs to...
14 comments posted 20yrs
posted by robin.bruce
14 comments posted 20yrs posted by robin.bruce