Hi Gang !
I am using ISE 8.1sp2 and ISE 7.1sp4 (same challenge with both versions).
I have an output bus, looks like this: FF->Comb. Logic->IOB This is a 8 bit bi-directional bus, and I am having a rally hard time meeting timing on it. I am convinced that the FPGA can actually do it, but I think I am not using the tools properly to their fullest capability.
The clock period for this bus is 16.6nS, the UCF file looks something like this: NET "phy_data" OFFSET = OUT 8.8ns BEFORE phy_clk;
The mapper thinks there is no timing problem, and reports:
COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -9.615ns |
0.815ns COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -9.631ns | 0.831ns COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -9.943ns | 1.143ns COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -9.982ns | 1.182ns COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -10.045ns | 1.245ns COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -10.069ns | 1.269ns COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -10.131ns | 1.331ns FORE COMP "phy_clk" | | |(slightly edited to fit better)
However, after P&R I get (in the par report):
- COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.362ns |
-0.438ns
- COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.634ns |
-0.166ns
- COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.667ns |
-0.133ns
- COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.753ns |
-0.047ns
- COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.783ns |
-0.017ns COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.849ns |
0.049ns COMP "phy_data" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.936ns | 0.136ns FORE COMP "phy_clk" | | |(slightly edited to fit better)
I tried several different options for the tools, like setting the overall effort to high, but it seems not to help.
It seems to me that it is a P&R problem, but if I could somehow tell the mapper to try to give me more slack on these IOs, it would also help.
What strategies, options, tricks, would you guys recommend for this problem ? I would really like to avoid using the FPGA editor and guide files, if at all possible.
The device is xc4vlx25, package sf363, speed -10, and is about
1/2 full with this design. All IOBs are locked.Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services,