Would anyone know where to get the JTAG programming specs (and programming times, page sizes, etc) for the XC18V01? I'd like to create an application for re-programming a 18V01 that takes as input the Intel Hex (MCS) and outputs JTAG bit banging. Xilinx recommends (app note 58 and 500) generating SVF or XSVF and using the XSVF player for the JTAG bit-bang. Unfortunately the memory requirements of this player are excessive.
So far most of my knowledge has been from studding the SVF file for the
18V01 that is generated by Impact - however - this isn't a good way to generate solid foundation for this project - and Xilinx has thus far been unwilling to provide these specifications.TIA, Chris
Section of SVF file that program's a page:
RUNTEST 1 TCK; RUNTEST 1 TCK; // Loading device with a 'faddr' instruction. SIR 8 TDI (eb) ; SDR 16 TDI (0060) SMASK (ffff) ; RUNTEST 1 TCK; RUNTEST 1 TCK; // Loading device with a 'fpgm' instruction. ENDIR IRPAUSE; SIR 8 TDI (ea) ; RUNTEST 1 TCK; RUNTEST 14000 TCK; // Loading device with a 'fdata0' instruction. SIR 8 TDI (ed) ; SDR 2048 TDI (0100401004010000000000000000000000000004010040100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000) SMASK (ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; ENDIR IDLE;XC18V01 BSD documents the following JTAG opcodes:
Attribute INSTRUCTION_OPCODE of XC1801 : entity is "BYPASS ( 11111111)," & "SAMPLE ( 00000001)," & "EXTEST ( 00000000)," & "IDCODE ( 11111110)," & "USERCODE ( 11111101)," & "HIGHZ ( 11111100)," & "CLAMP ( 11111010)," & "ISPEN ( 11101000)," & "ISPENC ( 11101001)," & "FPGM ( 11101010)," & "FADDR ( 11101011)," & "FVFY0 ( 11101111)," & "FVFY1 ( 11111000)," & "FVFY3 ( 11100010)," & "FVFY6 ( 11100110)," & "FERASE ( 11101100)," & "SERASE ( 00001010)," & "FDATA0 ( 11101101)," & "FDATA3 ( 11110011)," & "FBLANK0 ( 11100101)," & "FBLANK3 ( 11100001)," & "FBLANK6 ( 11100100)," & "NORMRST ( 11110000)," & "CONFIG ( 11101110)," &