need help on asynchronous buffer

The simplest solution is to make the whole asynchronous FIFO 16-bit wide, and build a simple synchronous "pre-assembler" that composes a

Peter Alfke, Xilinx (from home)

Thanks.

But the problem of the asynch-FIFO 16 is that I couldn't prevent simultaneous read and write. When the process tries to read and write at the same time by chance, the output is distorted.

How could I prevent this?

Thanks.

But the problem of FIFO16 is that I couldn't prevent simultaneous read and write.

When the process tries to read and write FIFO at the same time by chance, the output is distorted. The 'empty' signal doesn't much help, because the speed difference of input and output clk is large(about 10 times).

How do I prevent it?

You are sure you are using an async fifo from the core generator? And you connected the right clocks?

bye, Michael

You are using Virtez-2Pro CoreGen. Simultaneous read/write operations on the dual-ported Block-RAM are no problem whatsoever. Peter Alfke, Xilinx Applications

It is not clear to me why you think simultaneous read/write of the FIFO doesn't work. On the other hand, since you were talking about making your own buffer with a BRAM, that can be fairly easy to do when the clock rates of the input and output are fixed.

When the output clock is significantly faster than the input clock, I would normally take the least significant bit of input address, run it through a couple of synchronizer FFs at the output clock rate, and use transitions of it to generate an address. That address will follow slightly the input address, and will tell you where in the BRAM there is valid data.

Care must be taken that the two addresses are started cleanly for this to work. And if there is a need to reset the buffer during operation, that also must be handled carefully. If those conditions are difficult to meet, it might be desirable to use a true asynchronous FIFO.

CoreGen assumes that the read and write clock (can be totally asynchronous) are free-running, and you control the writing and reading with the Enable signals. It also assumes that you stop writing when Full and stop reading when empty. If that does not work for you, you have done something wrong. Check your design. Peter Alfke

CoreGen assumes that the read and write clock (can be totally asynchronous) are free-running, and you control the writing and reading with the Enable signals. It also assumes that you stop writing when Full and stop reading when empty. If that does not work for you, you have done something wrong. Check your design. Peter Alfke