BRAM for virtex-4

Hi all, i am using the following code for BRAMs and i copied these instantiations from virtex-4 libraray.But still i am getting an error message when i am trying to implment it using xilinx ise7.1 on virtex-4 fpga.It is giving an error message like .ngd build failed.Can anyone help me in solving this problem.

thanks,

Regards Ramakrishna

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--

-- Title : LocalRAM

-- Design : LocalRam

-- Author : Khaleel

-- Company : George Mason University

--

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--

-- File : LocalRAM.vhd

-- Generated : Sat Dec 3 15:23:33 2005

-- From : interface description file

-- By : Itf2Vhdl ver. 1.20

--

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--

-- Description :

--

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--{{ Section below this comment is automatically maintained

-- and may be overwritten

--{entity {LocalRAM} architecture {LocalRAM}}

library IEEE; use IEEE.STD_LOGIC_1164.all; Library unisim; use unisim.all;

entity LocalRAM is port( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Wea : in STD_LOGIC; Web : in STD_LOGIC; En : in STD_LOGIC; GRE : in STD_LOGIC; selq : in STD_LOGIC; Ain : in STD_LOGIC_VECTOR(31 downto 0); Bin : in STD_LOGIC_VECTOR(31 downto 0); A_addr : in STD_LOGIC_VECTOR(8 downto 0); B_addr : in STD_LOGIC_VECTOR(8 downto 0); Bout : out STD_LOGIC_VECTOR(31 downto 0); A_M : out STD_LOGIC_VECTOR(31 downto 0); Data_out : out STD_LOGIC_VECTOR(31 downto 0) ); end LocalRAM;

--}} End of automatically maintained section

architecture LocalRAM of LocalRAM is

component RAMB16_S36_S36 -- synthesis translate_off generic( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_A : bit_vector := X"0"; INIT_B : bit_vector := X"0"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; SRVAL_A : bit_vector := X"0"; SRVAL_B : bit_vector := X"0"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST" ); -- synthesis translate_on port ( DOA : out STD_LOGIC_VECTOR (31 downto 0); DOB : out STD_LOGIC_VECTOR (31 downto 0); DOPA : out STD_LOGIC_VECTOR (3 downto 0); DOPB : out STD_LOGIC_VECTOR (3 downto 0); ADDRA : in STD_LOGIC_VECTOR (8 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); CLKA : in STD_ULOGIC; CLKB : in STD_ULOGIC; DIA : in STD_LOGIC_VECTOR (31 downto 0); DIB : in STD_LOGIC_VECTOR (31 downto 0); DIPA : in STD_LOGIC_VECTOR (3 downto 0); DIPB : in STD_LOGIC_VECTOR (3 downto 0); ENA: in STD_ULOGIC; ENB : in STD_ULOGIC; SSRA : in STD_ULOGIC; SSRB : in STD_ULOGIC; WEA : in STD_ULOGIC; WEB : in STD_ULOGIC ); end component;

Signal Aout : STD_LOGIC_VECTOR(31 downto 0); Signal Plow : STD_LOGIC_VECTOR(3 downto 0); Signal Pout : STD_LOGIC_VECTOR(3 downto 0); Signal Bin1 : STD_LOGIC_VECTOR(31 downto 0);

begin Data_out 'Z'); A_M X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_04 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_05 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_06 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_07 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_08 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_09 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0A =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0B =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0C =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0D =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0E =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_0F =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_10 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F =>

X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"000000000", INIT_B => X"000000000", INITP_00 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 =>

X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 =>

X"0000000000000000000000000000000000000000000000000000000000000000", SRVAL_A => X"0000000000", SRVAL_B => X"0000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST" ) -- synopsys translate_on port map ( DOA => Aout, DOB => Bout, DOPA => Pout, DOPB => Pout, ADDRA => A_addr, ADDRB => B_addr, CLKA => CLK, CLKB => CLK, DIA => Ain, DIB => Bin1, DIPA => Plow, DIPB => Plow, ENA => EN, ENB => EN, SSRA => Rst, SSRB => Rst, WEA => WEA, WEB => WEB );

-- enter your statements here --

end LocalRAM;

Reply to
bachimanchi
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I suggest you to use RAM inference instead, which is supported in ise7.1. You will find appropriate templates for all supported RAM types and modes in the XST user guide, section 2 (HDL coding techniques). best regards,

Manu

snipped-for-privacy@gmail.com a écrit :

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Reply to
manu

Virtex4 uses RAMB16 instead of RAMB16_Sxx_Sxx. It is more convenient for parameterized blocks. A little bit more awkward for straight instancing. Pay attention to the addressing for different sizes, it may not be intuitive.

Reply to
Ray Andraka

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