Ignoring hierachy while flagging false with with Xilinx flow.

Does anyone here know if it is possible either using XST or Synplify Pro to flag a small number of specific nets to be ignored timing-wise in future place and route without preserving heirarchy during synthesis?

Currently I'm using TIGs in my UCF file, but by the time the design has gone through XST/Synplify the nets I need to flag have dissapeared and my design is unrouteable. If I turn on heirachy preservation though, my design doubles in size and overmapps my target FPGA.

Any help appreciated.


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Have you tried putting the TIGs in your HDL source?

Regards, Allan

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Allan Herriman

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Ken McElvain

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