Field-Programmable Gate Arrays

Virtex 4 deconfiguring itself ...

Hello, We're currently working on a design running on a Virtex4 SX35. That design uses most of the resources of the FPG...

3 comments posted 20yrs

posted by SomeOne

3 comments posted 20yrs posted by SomeOne

Ace file for design with dual ppc405

I'm currently using the Xilinx ML310 development board. Anybody knows how to generate ace file for designs with dual ppc...

5 comments posted 20yrs

posted by king.azman

5 comments posted 20yrs posted by king.azman

Simulation tool

Hi, What simulation tool will enable me to read internal signals/registers?

3 comments posted 20yrs

posted by adventleaf

3 comments posted 20yrs posted by adventleaf

Microblaze to My IP-Core connection

Hi, I created my test IP-core (ANDgate) on ISE and imported it to XPS t connect it to the microblaze. I am using Sparta...

0 comments posted 20yrs

posted by awetyemane

0 comments posted 20yrs posted by awetyemane

FATAL_ERROR while creating a test bench waveform (ISE WebPack 8.1.01i)

Hi, I am getting the following error when trying to add test bench waveform to one of my design files. After that, ISE...

2 comments posted 20yrs

posted by bobrics

2 comments posted 20yrs posted by bobrics

Fixed vs Float ?

Hello all, Concerning digital filters, particurlarly IIR filters, is there a preferred approach to implementation - Are...

10 comments posted 20yrs

posted by rover8898

10 comments posted 20yrs posted by rover8898

PacoBlaze with multiply and 16-bit add/sub instructions

Hello people. As I announced some days ago, I updated the PacoBlaze3 core [http://bleyer.org/pacoblaze/] now with a wid...

9 comments posted 20yrs

posted by pablobleyer

9 comments posted 20yrs posted by pablobleyer

ignore thread

All, I found that mozilla email supports a really useful feature: it is "ignore thread." I know, everyone else probably...

4 comments posted 20yrs

posted by austin

4 comments posted 20yrs posted by austin

Xilinx programming cable; Linux notebook w/o parallel port; Am I doomed?

Hi, I bowsed through some threads about using the various Xilinx programming cables. It seems like with my Linux notebo...

12 comments posted 20yrs

posted by GHEDWHCVEAIS

12 comments posted 20yrs posted by GHEDWHCVEAIS

DDS

I would like to implement a DDS on a Spartan device. Here are is my spec Clocked at 200MHz. Max Output of 80MHz. 1uHz in...

13 comments posted 20yrs

posted by maxascent

13 comments posted 20yrs posted by maxascent

SMTP

hello, I have to do a program in VHDL which sends email via the SMTP protocol on the Pegasus board. I have to use the X...

0 comments posted 20yrs

posted by leibnizster

0 comments posted 20yrs posted by leibnizster

Looking for a V4FX development board

Hi, I'm looking for a V4FX devel. board, with both optical (e.g. SFP)MGTs and ddr2 memory (especially one with DIMM mod...

2 comments posted 20yrs

posted by gpouikli

2 comments posted 20yrs posted by gpouikli

What are the major difference between MXE 6.0 and MXE 5.7?

I am using the MXE 5.7 with free license, but sometimes it seems unable to handle too large designs. What are the main u...

1 comments posted 20yrs

posted by novice

1 comments posted 20yrs posted by novice

VHDL LUT

Hi, Can anybody please tell me what is wrong with the following code? In post-translate simulation there are a few unex...

2 comments posted 20yrs

posted by alastairlynch

2 comments posted 20yrs posted by alastairlynch

Start Your Free Blog

Hi, I setup an account at http://www.bloggerteam.com the site provides quality blog hosting services with quality edita...

0 comments posted 20yrs

posted by webconf

0 comments posted 20yrs posted by webconf