Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

ChipScope and the FPGA Editor ILA command

Hi, I've been experimenting using the FPGA Editor to modify ChipScope monitor/trigger signals and reduce the requiremen...
1 comments posted 20yrs
posted by vivian.bessler.nospam
1 comments posted 20yrs posted by vivian.bessler.nospam

Quartus and Cygwin X-server

Hi! I'm running Quartus in remote Linux workstation and I use Cygwin X-server in my PC. If I use gnome desktop (xwin -q...
3 comments posted 20yrs
posted by antti.tyrvainen
3 comments posted 20yrs posted by antti.tyrvainen

ISE sends sensitive information to Xilinx site!

This afternoon I run a flow (ISE 8, Linux) and got in the log a warning message. The word 'Warning' was an hyper link s...
44 comments posted 20yrs
posted by cairosearch
44 comments posted 20yrs posted by cairosearch

problem programming Altera Cyclone device

Hello everyone, I am trying to program an Altera Cyclone (EP1C20) device, which comes with the NiosII processor already...
8 comments posted 20yrs
posted by roiavidan
8 comments posted 20yrs posted by roiavidan

how to readback a frame

hi all, I have a trouble in reading-back a frame of xcv1000e.According to xapp138,139,151,I wrote a .bit file and downl...
6 comments posted 20yrs
posted by harbinxiaoting
6 comments posted 20yrs posted by harbinxiaoting

Embedded Programming of Altera EPCS device

Has anyone out there been able to program an EPCS device via running code on a nios. The examples I find require an EPC...
0 comments posted 20yrs
posted by 42hammer
0 comments posted 20yrs posted by 42hammer

XdmHelpers:662

I am currently using ISE 8.1 and am receiving this message after entering a clock period constraint: WARNING:XdmHelpers...
0 comments posted 20yrs
posted by joel.weddick
0 comments posted 20yrs posted by joel.weddick

Report for routing resource usage?

Hello all: Is there a way in Xilinx ISE of knowing the percentage of routing resources that have been utilized after Pl...
3 comments posted 20yrs
posted by raarce
3 comments posted 20yrs posted by raarce

setting max fanout with xps flow

I want to constrain the max fanout for a particular net in my design. I am using the XPS flow and the net I want to con...
9 comments posted 20yrs
posted by notreally
9 comments posted 20yrs posted by notreally

Stopping Quartus using multipliers?

I'm prototyping a design on an Altera NIOS evaluation board with an EP2C35. The design will eventually be targeted at a...
7 comments posted 20yrs
posted by nial
7 comments posted 20yrs posted by nial

System Generator Eval version for Malab R2006a

Hi, I know this is the not the exact place to talk about system generator but I felt that this is the closest one. I ha...
0 comments posted 20yrs
posted by kishore2k4
0 comments posted 20yrs posted by kishore2k4

fpga debug

Hi, how does debug work in with fpga? On common processor you can move from line to line of code, check variables value...
10 comments posted 20yrs
posted by marco
10 comments posted 20yrs posted by marco

Config XCF04S using iMPACT

Hi, I am traing to use iMpact to program Xilinx PROM XCF04S, but no success. When I read back the file from the PROM af...
0 comments posted 20yrs
posted by thomas.b36
0 comments posted 20yrs posted by thomas.b36