Metastability question (newbie)


Please excuse me posting a presumably lame question here, but despite a rather thorough search I can't find answers to two bothering questions.

  1. I understand that when, say, a D flop's input changes along with the arrival of the active clock edge, the flop is likely to go metastable. But assuming it does, what will happen when no timing violations occur on the next active clock edge (i.e. the flop's input is ready and steady). Will the flop remain metastable or will its output settle to the valid input?
  2. What happens if a metastable flop's output is presented to the following (in a chain) flop's input? Will it go metastable too? Or is its action undefined?

Regards, Tomasz Dziecielewski

Reply to
Tomasz Dziecielewski
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The odds of the flop remaining metastable decrease with time in the absence of a clock. The arrival of the next active clock edge (with correct setup and hold time for data) will end the metastable state.

State in a flipflop is maintained by a positive feedback loop, except during a very short time near the clock edge, when the input to the FF is transferred to the output of the FF. If the input is stable during this short time, output will be stable after the normal propagation delay, regardless of the previous state of the FF.

There is a low probability that the following flipflop will also go metastable. In buffered CMOS logic (almost anything modern), meta stability usually shows up as a slower output time. If this slower output causes the input to the next flipflow to change at just the wrong time, then that flipflop may go metastable.

-- Phil Hays(Xilinx)

Reply to
Phil Hays

Good qustions.

  1. On the next clock, with valid and stable data on D, the flip-flop will react normally.
  2. The metastable output of a modern CMOS flip-flop is actually not at a strange level, but it can change between 0 and 1 at an uncontrolled time. Therefore, the cascaded flip-flop has no reason to go metastable, unless (and this is very unlikely) its D input happens to change exactky at the "moment of truth" where the second flip-flop is being clocked. That moment of truth is a very tiny window, measured in femtoseconds ( millionth of a nanosecond). That's why cascading two flip-flops is the standard method to effectively avoid metastability. (Avoid means: reducing its probability to a tolerably low level) Look for the Xilinx app note XAPP094 .(Or google with my name) Peter Alfke, Xilinx Applications
Reply to
Peter Alfke

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