Hi!
I have a question regarding the VHDL's "after" keyword. I've read that it is not synthesizable but only used for simulation and I was wondering if this is true for real-world programs. I'm working with Xilinx Spartan-2 (so it's Xilinx's systhesizer in question) and I've connected a soft processor to an external memory chip via my VHDL memory controller but the design isn't working if I deselect CS at the end of a cycle. I attempted to create delays using afters, ie. "CS