Hello,
I'm trying to set PAL on adv7321, but the output signal is progressive timing mode. Does anybody know what is proper register setting (configuration) for interlaced mode (PAL or NTSC)?
Martha
ADV7321 interlaced mode
May 26, 2006
2 Replies
Are you trying to initialize for 720 x 576 at 25 Hz frame rate with a
29.5 Mhz clock? And, how are you initializing the SD registers?Are you designing your own core and licensing a commercial core?
Derek
Clock : 27Mhz
Mode select reg (subadr: 0x01) - val=0x03 // SD only SD mode reg (subadr: 0x40) - val=0xED // PAL B,D... and filters
I also set color bars in SD mode reg 3 Timing is set to PAL: Fsc0 to Fsc4
I've got Xilinx VIODC and trying get test color bar.
marta
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