Hi, I am using the VirtexII DCM in my design to generate the master clock for all the modules in my design. The input freq is 20.48 MHz and the output freq from DCM is 61.44 MHz. The "LOCKED" signal from DCM is AND'ed with the system reset and given as reset to all the modules in the design. When I generate the DCM using Coregen, there is a option "wait for DCM lock before DONE signal goes high" when I click the "Advanced" button. Can anyone clarify me what will happen if I dont check this option ? Will it affect the startup operation or the functioning of the FPGA after startup? What is the significance of this option? When I check this option, I am getting a message that I should specify a value for LCK_dll in the bitgen options. First of all, I am not finding any option on that name in bitgen. I felt that the "Release DLL" option maybe the LCK_dll option which the ISE tutorial refers to. Plz let me know whether I am correct. I also dont know what value I should enter for this LCK_dll option. How to decide on the number of clock cycles?
Thanks & Regards, Srini.