Field-Programmable Gate Arrays

SPI c source code to shift register from apex board..

dear all... i m trying to write c cource code for my SPI connection . i m done creating cpu architecture in Apex board...

0 comments posted 20yrs

posted by didier_ja

0 comments posted 20yrs posted by didier_ja

Large Spartan3 vs. Small V5

So is Xilinx working on another budget-line FPGA? Or are they intending that small V5 chips replace the Spartan line al...

17 comments posted 20yrs

posted by brannonking

17 comments posted 20yrs posted by brannonking

Webpack ISE simulator error

I recently downloaded and installed XIlinx's Webpack ISE, version 8.2. I have been trying to work throught the quick st...

2 comments posted 20yrs

posted by no_spam_me2

2 comments posted 20yrs posted by no_spam_me2

Alternative for Mentor''s HDL Designer

Impossible in replaying to the newsthread "ModelSim Designer", I'd like to place my quastion here: Is the a free tool t...

8 comments posted 20yrs

posted by fpgaengineerfrankfurt

8 comments posted 20yrs posted by fpgaengineerfrankfurt

Spartan 3 Mask Code determination

Dear all, I apologise if this is an FAQ, but can someone point me in the direction of a document that allows me to go f...

0 comments posted 20yrs

posted by petermendham

0 comments posted 20yrs posted by petermendham

Bit-Serial Design with Xilinx System Generator

Hi, I have a question regarding the way the Xilinx blockset interprets wires: Are they considered to be parallel or ser...

0 comments posted 20yrs

posted by mmkhajah

0 comments posted 20yrs posted by mmkhajah

XILINX XAPP694

Hi, i'm trying to put my data into the PROM on the spartan 3 Starter Kit Board. I followed the instructions in XAPP694...

1 comments posted 20yrs

posted by sutejok

1 comments posted 20yrs posted by sutejok

IIR filter example ?

Does anyone knows where I can find an example of an IIR filter in VHDL ? = It is incredible, I can't find one on google....

7 comments posted 20yrs

posted by Erik.Verhagen

7 comments posted 20yrs posted by Erik.Verhagen

Microblaze power estimation with external memory..

Hi guys, I'm trying to design a very simple system based on Microblaze. I can do Post Place and Route simulation if I h...

1 comments posted 20yrs

posted by amirhossein.gholamipour

1 comments posted 20yrs posted by amirhossein.gholamipour

chipscope_opb_iba woes in XPS EDK

Has anyone out there had success instantiating chipscope cores in XPS? I have a V4FX design that builds with no problem...

3 comments posted 20yrs

posted by jcc

3 comments posted 20yrs posted by jcc

Crystal input for FPGA

I am posting this just as a suggestion for future FPGAs. It would be nice if a crystal can be connected to FPGA to prov...

25 comments posted 20yrs

posted by shrutisumit

25 comments posted 20yrs posted by shrutisumit

[Xilinx] MIG V1.6 Reduced max Speed for DDR2 controllers ??

Hi all, working on DDR2 controllers generated with MIG V1.6 I did notice the reduction in max speed for "Direct Clockin...

0 comments posted 20yrs

posted by meng.engineering

0 comments posted 20yrs posted by meng.engineering

Error building mpmc2

Hello all, In my quest to evaluate multicast performance on the ML403 board I have downloaded the mpmc2 example. I am a...

1 comments posted 20yrs

posted by jpriceelvis.removeme.andme

1 comments posted 20yrs posted by jpriceelvis.removeme.andme

Spartan3 dev board... will USB keyboard work?

Hello, Will a USB keyboard work with the Spartan3 dev board? I know that USB keyboards will work with a PS2 connector o...

1 comments posted 20yrs

posted by aiiadict

1 comments posted 20yrs posted by aiiadict

RocketIO MGT Tile/Column Question

Dear all, I am struggling to find the information I need from the Xilinx datasheet, perhaps someone could provide me wi...

6 comments posted 20yrs

posted by petermendham

6 comments posted 20yrs posted by petermendham