Field-Programmable Gate Arrays

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RocketIO MGT Tile/Column Question

Dear all, I am struggling to find the information I need from the Xilinx datasheet, perhaps someone could provide me wi...
6 comments posted 20yrs
posted by petermendham
6 comments posted 20yrs posted by petermendham

Video - DSP Eval board with Altera

Is there anybody out having experiences with an evaluation board, containing an Altera FPGA like Cyclone or Stratix and...
3 comments posted 20yrs
posted by fpgaengineerfrankfurt
3 comments posted 20yrs posted by fpgaengineerfrankfurt

Microblaze : Timingproblems

Hello, I'm still working on my diploma thesis with uC/OS and the Micrium TCP/IP Stack. I'm working with the Ml403 Xilin...
0 comments posted 20yrs
posted by
0 comments posted 20yrs posted by

How to attach module to the design source?

Hi, Just to learn VHDL, I cannot understand a problem with the example stopwatch VHDL coming with Xilinx webpack 8.2. I...
1 comments posted 20yrs
posted by rxjwg98
1 comments posted 20yrs posted by rxjwg98

Xilinx Webpack inferring BRAMS, RedHat version

I have been working on a design that uses BRAMs to implement a register file using the Windows version of the Xilinx We...
0 comments posted 20yrs
posted by jerwood
0 comments posted 20yrs posted by jerwood

Altera Cyclone-II FIFOs

Hi, I have some problems with async clocked FIFOs in Altera Cyclone-II. When simulating the design I receive data out f...
1 comments posted 20yrs
posted by michael_laajanen
1 comments posted 20yrs posted by michael_laajanen

Problem of uninstall modelsim

Hi, I have installed Xilinx webpack and modelsim in my computer. I find it is rather perhaps because of the memory not...
1 comments posted 20yrs
posted by rxjwg98
1 comments posted 20yrs posted by rxjwg98

Virtex 4 could not work correct,is it damaged?

One chip of Virtex 4,SX35F668,is used in my PCB board,When the board is first assembled,the FPGA could performance very...
3 comments posted 20yrs
posted by Borry.Wang
3 comments posted 20yrs posted by Borry.Wang

Maximum Current Draw of FPGA

I've reviewed the docs briefly but didn't find this information. I'm playing with a XC3S400 in a 256 BGA on the Digilen...
28 comments posted 20yrs
posted by nevo_n
28 comments posted 20yrs posted by nevo_n

dynamic fpga via bytecode sequence?

hi designing an open and free specification IC (OFSIC) and am wondering of the possibility of a bytecode for programmin...
0 comments posted 20yrs
posted by jackokring
0 comments posted 20yrs posted by jackokring

virtex II inner organisation

Hi everyone, I'm trying to deal with readback and scrubbing into a XC2V1500 FPGA. I've got a problem identifying the Ma...
4 comments posted 20yrs
posted by tnerolf
4 comments posted 20yrs posted by tnerolf

Repost: ISE Webpack 8.1 adder wierdness

It appears my 1st attempt didn't make it through :( The first two examples produce 16 4-input LUTs on a Spartan 3 and t...
1 comments posted 20yrs
posted by tbfleming
1 comments posted 20yrs posted by tbfleming

Xilinx V4FX Embedded MAC.

Hi, I was wondering if someone who has used the embedded MAC's can give me a pointer here. I am using BaseX mode, with...
0 comments posted 20yrs
posted by marc
0 comments posted 20yrs posted by marc

ISE Webpack 8.1 adder wierdness

The first two examples produce 16 4-input LUTs on a Spartan 3 and the third produces only 8 4-input LUTs. Is there a wa...
7 comments posted 20yrs
posted by tbfleming
7 comments posted 20yrs posted by tbfleming