Large Spartan3 vs. Small V5

So is Xilinx working on another budget-line FPGA? Or are they intending that small V5 chips replace the Spartan line altogether? What's their next budget chip with the new LUT structure and when can I look for it?

According to Xilinx's website, the Spartan-3E line is for gate-centric uses and goes up to 1.2M gates. Yeah. Huge.

I just finished a project that uses 4.5M gates (so says the MRP) on each of eight 2v6000 chips. It's only using 1/3 the block RAM and none of the MUL blocks on any chip. It only accesses DRAM from one chip. I want that project on cheap hardware. What chips would you recommend for this? By cheap I mean $40/chip, not $2000/chip.

Reply to
Brannon
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Maybe that's the problem. Can you move any of your storage into block ram and do serial processing?

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Ben Jackson AD7GD

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Reply to
Ben Jackson

Howdy Brannon,

What is your target production date? Next week (need to use S3 or V4) or early next year (in which case, you can consider *some* V5's)? I assume that since you are considering V5, you don't have any restrictions on your power rail(s), and they can be made to be relatively clean. Life-span of the product and number of devices needed per year would probably also figure into how much it makes sense to stay in standard FPGA vs. an easy path approach.

Lastly, "4.5M gates" doesn't mean much. Is that 55k LUTS?

My WAG is that your least expensive alternative is probably an XC3S4000.

Good luck,

Marc

Reply to
Marc Randolph

Here is a shot at it,

See below,

Austin

-snip-

Yes. Always. It is "our business."

Or are they intending

No. We sorted that out, the Virtex line is no longer interested in "small" parts.

What's their

I can't tell you something like that! One thing you can always count on: Moore's Law. Is 65nm smaller and cheaper? Yes. And 45nm, yes again. And so on.

For some, yes, others not. It is all about marketing. Sell to the ones who have the money. Cost of mask set, etc. How many did you want?

Congratulations on your accomplishment...

What chips would you recommend for

Well, four 2V6000s is now proabably replaced by 5VLX220. That doesn't include any intelligent re-targeting to structures that are better suited (ie more compact) or design changes to fit it into a smaller device. 5VLX220 will not be "introduced" until later (just keep watch on the announcements).

As for less than $40 (for a LX220), well, that doesn't seem likely, even at 65nm.

Maybe next time? From the Virtex 1000, to the Spartan 3S1000, the price to the user has diminshed by more than two decades (for the same, or more, logic).

Reply to
Austin Lesea

Since you do not use MULs and only little BRAM, the V4LX series would make sense - more logic, much fewer specialized (BRAM/DSP) resources and less expensive than their V2 equivalents... but nowhere near $40/chip though.

Unless there are specific reasons why you need the 3E, the plain '3' go up to ~5M gates but even that still costs way more than $40/chip: I checked out prices on avnet, XC3S5000-4FG1156C = $390 each.

Reply to
Daniel S.

This project is to outrun serial processors, which it does by doing lots in parallel. It is not doing much in the way of storage. Think software acceleration, not ASIC prototyping.

Reply to
Brannon

The boards with 2v6000 chips are already in production. I was thinking of this as a next-gen version of the hardware for somewheres about 8 months from now.

It uses 49k LUTS and the same number of FFs.

I probably need the 5000, and they are not as cheap as I'd like though significantly cheaper than 2v6000.

Reply to
Brannon

The series 3 are .13 micron, true? Is that why they're (debateably) expensive?

Reply to
Brannon

Well, after looking at the charts again, maybe a 3s4000 would do it. Even the 2000 model is reasonably large. Unfortunately, the Webpack tool doesn't support any of those larger Spartan 3 chips. I had been hoping to find a chip solution that would allow product customers to customize their gateware using Webpack (because it's free for them).

Reply to
Brannon

Altera's Cyclone II family is fully supported by free tools and the largest (EP2C70) is about 68k LUT, much more than the 3S5000.

I don't know how the pricing compare though.

Tommy

Reply to
Tommy Thorn

spartan3 (and s3E) is 90 nm Aurash

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/ /\/\ Aurelian Lazarut
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Reply to
Aurelian Lazarut

IIRC, the 3E is the 'Economy' series, the 3L is the 'Low-Power' series and plain 3 is standard parts. Like others said, they all are 90nm.

BTW, if you are really wasting BRAMs, you could tell your synthesis tools to map logic into BRAM. If the older Vxxxx have anywhere near the V2P's BRAM-to-logic ratio, this would free up a bunch of LUT/FFs.

Me, I am holding my breath until the V5SXes come out - I am hoping for

12xRocketIO for the price of 8 on V4.
Reply to
Daniel S.

I think you may have proposed a great plan. Their prices range from $125 to $300 for their 672 pin chips (according to their website). That's still three times what I had been hoping for, but maybe I could make that work. And it is 25% cheaper than Xilinx. Can I get these Cyclone II chips for less than that through some other dealer?

Reply to
Brannon

Glad to be of (self-) service :-) I might be a taker if it has big enough devices (insert my usual plea for lots of RLDRAM II memory).

Tommy

Reply to
Tommy Thorn

Is it impossible to make the project use 1.25M gates on each of thirty-two 3S1500 chips?

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is the sort of hardware that I imagine targetting when contemplating cheap FPGA approaches to problems.

Tom

Reply to
Thomas Womack

Brannon

On current technology you would be very lucky to make $40/chip mark for something the size of a 2V6000 unless you have a very high volume. Even then I'm dubious.

However it is worth examining your design to see if it can be crushed to allow smaller cheaper parts to be used. I have seen designs reduced by 40-50% in some cases by a good designer. Playing with tool settings can give you something but the best I have seen is in the order of

10-15% reduction by this approach.

Another thing to consider is sharing of resources to reduce size e.g. a multiplier servicing 2 data streams in a time muxed fashion.

Also for the brew is the fact that the biggest devices come at a premium and several smaller devices of the equivalent logic size may be cheaper.

It is also worth looking at the ram to logic ration of the chip you use. RAM is a relatively expensive resource in a FPGA so using a FPGA that is less memory rich may bring benefits. Typically the lower end families have a lower ram/logic ratio. Even within families you will find variations in the ration so choosing an appropraite size may help cost too.

John Adair Enterpoint Ltd.

Brann> So is Xilinx working on another budget-line FPGA? Or are they intending

Reply to
John Adair

I was talking to a rep the other day and he pointed out that "there is no minimum pricing for FPGAs". Now we know that is not really true, but the point is that if you speak with the disti or the manufacturers account manager, they will be willing to "bid" on your business much more so than other semi manufacturers. There seems to be a very high markup on FPGAs and if you buy in any volume they will give you some good pricing. I have seen this first hand where I was given 50,000 piece pricing for 1,000 piece quantities in order to get the design win.

So don't worry about web pricing, it is typically not very good. Get the disti involved and you can get some much better pricing.

Reply to
rickman

The more chips you have, the more IOs you need to stitch them together unless the data dependencies are highly linear, clean and somewhat minimalist. Otherwise peak attainable performance quickly becomes IO-bound.

In the case of code-breaking applications, as long as you pick FPGAs large enough to contain at least one instance of the code-breaking unit, you will not need to worry about interconnects. The rest is simply a matter of setting performance targets, selecting an FPGA family then cost-optimize the device count, size (number of code-breaking units per FPGA vs device cost) and speed grade - code-breaking is generally so parallelizable that there is very little to no performance gain between a single large-scale system and N N-times as slow smaller-scale ones.

Reply to
Daniel S.

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