hi
why not have the one fixed max frequency on chip, and have a programmable divider to get a subfrequency
if this must be locked to an external clock, the factors are the high capacitance of the crystal, necessitating, a big drive inverter/buffer (XTAL0), which works at high frequency. and enough gain on (XTAL1 pin) that positive feedback occurs.
a chain of three inverters, will provide squareish wave.
to avoid problems of offset drift in the high impedance of XTAL1 pin it is required that some kind of very small hysterysis (+ve feedback through resistance) after two of the tree inverters is mixed on chip with the XTAL1 in signal, as this flots the XTAL1 pin arround 1/2 supply.
the first inverter has to have long channels to reduce power disipation and the last has to have wide channels to drive the XTAL0 pin.
the middle one should make the three a gemetric progression of on resistance.
a differential pair would make a better comparator for the first inverter, with lower power consumption, and the ability to apply an integration of the signal in as negative feedback to reduce the hystresys needed, which in turn aids starting of the oscillator.
basic rule is keep external osc frequency low (less slew rate problems and power dissipation problems), and use a fully digital lock loop (PLL actually frequency locked loop) based on gate delays as the on chip oscillator (must use high resistance inverters for low power, which make longer delay), and use a divider counter to effect VCO.
this solution has much jitter, but in most cases external bus speeds are slower than internal ones, and so the jitter % is small.
formatting link
for an open hardware initial CPU specification document, still being written.
Cheers
jacko