[Xilinx] MIG V1.6 Reduced max Speed for DDR2 controllers ??

Hi all,

working on DDR2 controllers generated with MIG V1.6 I did notice the reduction in max speed for "Direct Clocking Mode"

Up to now a speedgrade -11 LX60 Virtex-IV device did support up to

Using the MIG V1.6 that has some fixes this technique can only be used for ~210 MHz, a reduction of 20% in speed.

I haven't found any information on the Xilinx Web-Site why this is so.

I get the impression that from the beginning on up to now, Xilinx did reduce the max speed for their devices from time to time.

The problem I face, is that we have boards that require at least 250 MHz in Direct Clocking Techniques Mode, and I really would like to understand, why Xilinx did this reduction in terms of max speed using a 512MBit DDR2 from Micron -37.

Any Idea?

Best Regards Markus

BTW the post layout simulation on the DDR2 controllers with a build in Testbench is not working properly. On the Data Mask pins after calibration, these signals drive XX and the comparison fails. Seems to be in the Sim Library ...