Field-Programmable Gate Arrays

ask for help about routing/unrouting problems in jbits2.8,thanks

Hi all, Now, I am trying to using Jroute2 to do some routing things. But I am blocked by some questions. 1\ find all th...

0 comments posted 19yrs

posted by harbinxiaoting

0 comments posted 19yrs posted by harbinxiaoting

Post-route simulation

I'd like to check timing of my cicrcuit.. I have chosen post-route simulation... does it show how it works in real devi...

0 comments posted 19yrs

posted by spawnek

0 comments posted 19yrs posted by spawnek

placing addiional caps across existing caps to reduce noise

To the subject at hand: placing additional caps across existing caps does not reduce the noise (unless the dominant cau...

83 comments posted 19yrs

posted by austin

83 comments posted 19yrs posted by austin

Question about library update in Modelsim

Hi, I am learning Modelsim 6.1e XE coming from ISE webpack. In its tutorial lesson 4, it gives an example about creatin...

1 comments posted 19yrs

posted by rxjwg98

1 comments posted 19yrs posted by rxjwg98

Quartus software and dual-purpose pins

I'm designing a Cyclone device and am having problems with one pin. I want to use the configuration pin ASDO as an I/O...

3 comments posted 19yrs

posted by nevo_n

3 comments posted 19yrs posted by nevo_n

is ISE coded in Java?

Hi, dears: I am heard that ISE is coded in Java. So it is very flexible when migeration but is very slow. Is it true?

2 comments posted 19yrs

posted by pldhacker

2 comments posted 19yrs posted by pldhacker

Problem with netlister in System Generator

Hello, I am newbie learning Xilinx system generator. I have made a simple down sampler program which will just downsamp...

3 comments posted 19yrs

posted by sivakanth.telasula

3 comments posted 19yrs posted by sivakanth.telasula

adiabatic and reversible computing with FPGAs?

Is it possible to use adiabatic computing with today FPGAs? It uses less power by stretching the time for loading capac...

0 comments posted 19yrs

posted by fb

0 comments posted 19yrs posted by fb

What is the truth about the Virtex5 ?

I questioned the availability of the Virtex5 back in July on this group and got some responses from Xilinx people sayin...

14 comments posted 19yrs

posted by jeffnewcomb

14 comments posted 19yrs posted by jeffnewcomb

How to change the font size in text editor of modelsim

Hi, I am using Modelsim 6.2e with the Xilinx webpack 8.2. When I print the vhdl text from the text editor of Modelsim,...

1 comments posted 19yrs

posted by rxjwg98

1 comments posted 19yrs posted by rxjwg98

FPGA -> SATA?

I am looking for a way to read/write to a SATA drive from an FPGA. I've looked around. Nothing seems to fit the bill. A...

51 comments posted 19yrs

posted by x

51 comments posted 19yrs posted by x

I2C on Xilinx Virtex-4/ML403

I'm developing on an ML403 evaluation board with a Virtex-4 device. I'm calling Xilinx's Level 0 I2C driver routines (X...

7 comments posted 19yrs

posted by eckardts

7 comments posted 19yrs posted by eckardts

Virtex 4 TEMAC and MII questions

Hello, I have to design a ethernet link in a V4 to be interfaced to an external PHY with a MII interface. The ethernet...

1 comments posted 19yrs

posted by t

1 comments posted 19yrs posted by t

Installing Quartus 6 "web edition full"

Is there a difference between Quartus "Web Edition" and "Web Edition Full"? I bought the NIOS development kit which cam...

2 comments posted 19yrs

posted by edaudio2000

2 comments posted 19yrs posted by edaudio2000

UltraController II + SystemAce

Hello everyone, First of all, big thanks to everyone who contribute to this newsgroup. Most of the time, I can find a s...

12 comments posted 19yrs

posted by prdubois

12 comments posted 19yrs posted by prdubois