Hello,
I am newbie learning Xilinx system generator.
I have made a simple down sampler program which will just downsample the incoming signal and presents it as downsampled version.
The simulink simulation runs well, but when I try to create a HDL netlist, the process just hangs in "Running Netlister".
Can someone help with this issuse and can provide a solution.
Sivakanth.
snipped-for-privacy@gmail.com ha scritto:
Hi,
Try to restart Matlab and delete the '.\netlist' directory. My design (with sysgen 8.1) work correctly.
Hello,
The suggestion you have made didn't work. I couldn't find a suitable solution even in the answers database of xilinx.
Sivakanth
snipped-for-privacy@gmail.com wrote:
Hello,
I found the solution at Xilinx answer record # 23274
I hope this will be help for other people
Sivakanth
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