I'd like to check timing of my cicrcuit.. I have chosen post-route simulation... does it show how it works in real device?
I use clock from DCM.. there is BUFG on output.. BUFG makes good routing, correct? I used it one more time
In DCM I generate clock for memory.. How should I tranport this signal?
From DCM by new BUFG:(?)
BUFG_INST : BUFG port map (I=>DCM_OUTPUT_CLOCK, O=>CLK_FOR_MEMORY);
I think better is giving clock from component which gives data and signal controls because path for clock and signal controls will be the same.
DCM_OUTPUT_CLOCK = > Component_DRIVER => BUFG => CLK_FOR_MEMORY2
If I make both, CLK_FOR_MEMORY is different than CLK_FOR_MEMORY2.
And the best is: signal sensitived of DCM_OUTPUT_CLOCK, is earler on output than CLK_FOR_MEMORY2 and CLK_FOR_MEMORY. (If i use BUFG).
I do not know if BUFG is necessary... I saw that BUFG delays my clock and I am happy because memory wants to get controls signal before rising clock.
If someone can tell me anything, I will be gratefull :-)