Field-Programmable Gate Arrays

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Error message in ISE7.1

Hi, anyone ever had something like this: "ERROR:Xst:800 - "C:/MyFolder/control_unit_top.vhd" line 317: Multi-source on...
1 comments posted 19yrs
posted by marco
1 comments posted 19yrs posted by marco

Xilinx IPIF DMA done interrupt ?

Hello group, I would appreciate help in capturing the DMA done interrupt. If anybody could point me to a working exampl...
1 comments posted 19yrs
posted by M.G.v.d.Horst
1 comments posted 19yrs posted by M.G.v.d.Horst

Linear priority encoder in Xilinx Virtex4

Hello, I need a linear priority encoder that has N input and N outputs. Searching the group, I saw a thread where Peter...
4 comments posted 19yrs
posted by SomeOne
4 comments posted 19yrs posted by SomeOne

RocketIO over cable

Anyone have experience with directly driving a cable with RocketIO? I am interested in any information/experiences/advi...
10 comments posted 19yrs
posted by vt2001cpe
10 comments posted 19yrs posted by vt2001cpe

Why isn't there a thermal diode on large FPGAs?

A recent thread went over the maximum permitted power on a device. So why don't we have a sensing diode (well, a transi...
10 comments posted 19yrs
posted by PeterSmith1954
10 comments posted 19yrs posted by PeterSmith1954

QuickLogic

Hi, I was thinking about using QuickLogic for a low power FPGA design. Does anyone have any experiences they would like...
3 comments posted 19yrs
posted by clevin1234
3 comments posted 19yrs posted by clevin1234

DDR controller on Spartan-3e 500

Hi, I want to control a 16 bit DDR module with the 256 pin Spartan-3e 500 package. There are too many pins on the DDR t...
2 comments posted 19yrs
posted by dash
2 comments posted 19yrs posted by dash

Xilinx BRAMs question - help needed ..

Hi all, My problem is as follows, I need to use a BRAM to create a true dual port memory (6x512). My memory should be w...
9 comments posted 19yrs
posted by me_2003
9 comments posted 19yrs posted by me_2003

Modelsim XE problem with Xilinx ISE 8.1i and 8.2i

This is an all VHDL design. Modelsim XE is installed as full VHDL. Design uses a number of block rams built with Xilinx...
0 comments posted 19yrs
posted by danielgkNOSPAM
0 comments posted 19yrs posted by danielgkNOSPAM

ISERDES strange simulation behaviour

In the Virtex-4 user guide (ug070.pdf p.365 table 8-4) it is clearly indicated that for INTERFACE_TYPE=NETWOKING and DA...
8 comments posted 19yrs
posted by taileb.mehdi
8 comments posted 19yrs posted by taileb.mehdi

high level languages for synthesis

Hi, What is your opinion on high level languages such as systems C, handel-C etc. for FPGA development instead of VHDL/V...
31 comments posted 19yrs
posted by jayasanka.piyaratna
31 comments posted 19yrs posted by jayasanka.piyaratna

Why No Process Shrink On Prior FPGA Devices ?

I'm wondering what intrinsic ecomomic, technical, or "other" barriers have precluded FPGA device vendors from taking th...
22 comments posted 19yrs
posted by cmusial
22 comments posted 19yrs posted by cmusial