Hello,
I have to design a ethernet link in a V4 to be interfaced to an external PHY with a MII interface.
The ethernet link has to work in two ways :
- Normal transmit / receive through the TEMAC using the MII interface
- Manual driving of the MII interface from the FPGA logic to access the PHY with the the TEMAC disabled
- Going back to normal transmit / receive through the EMAC using the MII interface
- and so on
Here are my questions :
- Is the TEMAC hardware usable alone without any Ethernet IP ? How can this be done ?
- Is the MII interface part of the TEMAC or can thes MII interface signals be accessible from the rest of the FPGA, in parallel with the TEMAC ?
- Does the TEMAC logic can be connected / disconnected to the MII interface quickly and without having to reinitialize it ?
- Can a MII interface be accessible and driven with logic from inside the FPGA ?
Thank you for your answers.
Stéphane.