1. Home
  2. Field-Programmable Gate Arrays
  3. I2C on Xilinx Virtex-4/ML403

I2C on Xilinx Virtex-4/ML403

I'm developing on an ML403 evaluation board with a Virtex-4 device. I'm calling Xilinx's Level 0 I2C driver routines (XIic_Send, _Recv) from a PPC405 program running under the QNX OS. I'm connecting to an external I2C device, a temp sensor/ADC, via the J3 header on the ML403.

When scoping the I2C SDA and SCL lines, I often notice a missing bit within the 8-bit address word. Obviously, when this happens, the addressed device does not ACK the transfer.

I believe that my physical I2C connection is correct because I can successfully and consistently use the GPIO-I2C bit-banging approach (as implemented in Xilinx's iic_eeprom test program) to communicate with my external device.

I'm not sure how my operating environment or the driver could cause this problem. The address is supplied by a single byte-write to the OPB_IIC core's Tx FIFO register; that seems atomic to me. My gut feeling is that there is a problem with the core.

Anyone seen this problem, or know what I might be doing wrong??

Reply to
Suzie
Loading thread data ...

Suzie schrieb:

no, but I see another problem with the OPB_IIC core. no matter I set the clock scaler, etc the OPB_IIC core just gives me 650KHz clock out. on SDA line.

I have managed I think to get the OPB_IIC working too one a long time ago, but bitbang is way EASIER and always works.

Antti

Reply to
Antti

Are you saying that the output frequency of the SCL line is 650KHz? Mine is set for the default value of 100KHz, and the measured frequency is slightly lower at at approximately 90KHz.

I'm using the v1.01c and v1.01d cores; what are you using?

Reply to
Suzie

Suzie schrieb:

sorry, no. I tried the OPC_IIC and for some reason the core was totally crazy. there was continous free running clock on SDA line all the time. something was badly wrong. nothing todo with your problem. keep looking!

-- Antti

Reply to
Antti

The bit-banging is probably slower.

How are you handling your IOs?

You may wish to use tristate outputs with your signals going to the T input:

scl_iobuf : IOBUF port map ( O => open, IO => scl_pin, I => '0', T => scl_master );

sda_iobuf : IOBUF port map ( O => sda_slave, IO => sda_pin, I => '0', T => sda_master );

Brad Smallridge aivision dot com

Reply to
Brad Smallridge

Even after applying the IP core and driver patches described in Xilinx Answer 23866, I still have the same problem. What could cause the core to skip a bit/clock within a transfer that is atomic at the user-level?

Reply to
Suzie

Suzie,

you might want to try replacing R70 and R71 on the board with 1K resistors (currently 10K). While we are still looking into this issue it looks like the pull-up resistors are too weak resulting in a long rise time of SCL (and SDA).

- Peter

Suzie wrote:

Reply to
Peter Ryser

In limited testing following replacement of the R70 and R71 resistors, per Peter's recommendation, I have not seen the "missing bit" problem - nor other previously-seen problems with SDA or SCL being held low.

Reply to
Suzie

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.