Is it possible to use adiabatic computing with today FPGAs? It uses less power by stretching the time for loading capacitors and uses LC tanks for energy storage:
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The ultimate power reduction would be to use reversible computing:
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because in theory the energy dissipation is zero. You can use the Fredkin gate as the base gate for implementing all logics:
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which can be implemented with collision-based computing, like the billiard ball model:
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But how can this be implemented in ICs? Some ideas are presented in this article and one implementation of the Fredkin gate with collision-based computing elements:
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Are there any plans from the major FPGA vendors to incorporate some of these ideas in their devices?