Latest threads in Field-Programmable Gate Arrays

Altera CPLD 7128S heating up

Hi, I work on a board with an Altera 7128S part (5V quite old but still used ...). It seems the part is most of the tim...

6 20yrs

jfhasson

6 20yrs jfhasson

ddr with multiple users

Hi, I have about 4 different independent things that each need to access a ddr. On one hand it seems I can make them al...

27 20yrs

dash

27 20yrs dash

Synchronous Clocks

How do we apply a constrain to the Xilinx PAR tool to let it know that two clocks in the design are synchronous, and so...

3 20yrs

szohair

3 20yrs szohair

Certify partition tool for FPGAs

Hi , I am looking at tools to partition design onto Multiple FPGAs. Please let me know if anyone used/uses Certify and i...

0 20yrs

sandesh.bharadwaj

0 20yrs sandesh.bharadwaj

2 FF synchronizer

Hi, Kindly clarify the following doubts on Two FF synchronizer. Most of the material available in net says the two flip...

3 20yrs

himassk

3 20yrs himassk

RTL deisgn for Blocking and Nonblocking

Hi, Please clarify me about blocking and nonblocking statement difference in RTL design. CODE1: always@(X or Y or Z) beg...

1 20yrs

himassk

1 20yrs himassk

Xilinx Impact Cable Drivers for 64-bit Linux?

Has anyone gotten Xilinx Impact to work under 64-bit Linux? Has Xilinx released Linux kernel 2.6 drivers for 64-bit? Th...

1 20yrs

cole

1 20yrs cole

Altera simulation model

Hi, I am doing simulation with Altear FPGA Clone II. Now I need to do some multiply and fifo simulation, but I can't fi...

1 20yrs

chenyong20000

1 20yrs chenyong20000

Xilinx LogiCORE PCI32

where I can read about use PCI-core user application signals? I use this core in target mode. I whant to do standart mic...

5 20yrs

axalay

5 20yrs axalay

Bitgen warning message DCM

Hello, in my design for a Spartan 3 4000 FG676-4 I have included a DCM that = synthesizes a clock of 20 MHz out of exte...

0 20yrs

phoenix44

0 20yrs phoenix44

how can I decrease the time cost when synthesis and implement

hi, all I am developing a design with V4 LX100, and the project is large, which usually cost me 2 hours to synthesis an...

11 20yrs

frogkinger908

11 20yrs frogkinger908

Zigbee mesh sensor network

We have a wired Spartan-3 based sensor unit and want to make it wireless. We'd like to have a mesh network with 100-100...

0 20yrs

zcsizmadia

0 20yrs zcsizmadia

BUFR in timing sim not working

I have a setup that is passing behavioral sim but not timing sim. The basic setup is as follows. I have a 100 MHz clock...

0 20yrs

mottoblatto

0 20yrs mottoblatto

TI TFP410 DVI transmitter help?

I am trying to use I2C to configure TI TFP410 DVI transmitter. I put differential clock input and VSYNC/HSYNC with the...

5 20yrs

ssc3k

5 20yrs ssc3k

Xilinx Spartan 3 Configuration

Hi i have 3 X Spartan 3 to configure i followed the Master Serial configuration from the application note, but the samp...

0 20yrs

yy7d6

0 20yrs yy7d6

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