Field-Programmable Gate Arrays

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ddr with multiple users

Hi, I have about 4 different independent things that each need to access a ddr. On one hand it seems I can make them al...
27 comments posted 19yrs
posted by dash
27 comments posted 19yrs posted by dash

Synchronous Clocks

How do we apply a constrain to the Xilinx PAR tool to let it know that two clocks in the design are synchronous, and so...
3 comments posted 19yrs
posted by szohair
3 comments posted 19yrs posted by szohair

Certify partition tool for FPGAs

Hi , I am looking at tools to partition design onto Multiple FPGAs. Please let me know if anyone used/uses Certify and i...
0 comments posted 19yrs
posted by sandesh.bharadwaj
0 comments posted 19yrs posted by sandesh.bharadwaj

2 FF synchronizer

Hi, Kindly clarify the following doubts on Two FF synchronizer. Most of the material available in net says the two flip...
3 comments posted 19yrs
posted by himassk
3 comments posted 19yrs posted by himassk

RTL deisgn for Blocking and Nonblocking

Hi, Please clarify me about blocking and nonblocking statement difference in RTL design. CODE1: always@(X or Y or Z) beg...
1 comments posted 19yrs
posted by himassk
1 comments posted 19yrs posted by himassk

Xilinx Impact Cable Drivers for 64-bit Linux?

Has anyone gotten Xilinx Impact to work under 64-bit Linux? Has Xilinx released Linux kernel 2.6 drivers for 64-bit? Th...
1 comments posted 19yrs
posted by cole
1 comments posted 19yrs posted by cole

Altera simulation model

Hi, I am doing simulation with Altear FPGA Clone II. Now I need to do some multiply and fifo simulation, but I can't fi...
1 comments posted 19yrs
posted by chenyong20000
1 comments posted 19yrs posted by chenyong20000

Xilinx LogiCORE PCI32

where I can read about use PCI-core user application signals? I use this core in target mode. I whant to do standart mic...
5 comments posted 19yrs
posted by axalay
5 comments posted 19yrs posted by axalay

Bitgen warning message DCM

Hello, in my design for a Spartan 3 4000 FG676-4 I have included a DCM that = synthesizes a clock of 20 MHz out of exte...
0 comments posted 19yrs
posted by phoenix44
0 comments posted 19yrs posted by phoenix44

Zigbee mesh sensor network

We have a wired Spartan-3 based sensor unit and want to make it wireless. We'd like to have a mesh network with 100-100...
0 comments posted 19yrs
posted by zcsizmadia
0 comments posted 19yrs posted by zcsizmadia

BUFR in timing sim not working

I have a setup that is passing behavioral sim but not timing sim. The basic setup is as follows. I have a 100 MHz clock...
0 comments posted 19yrs
posted by mottoblatto
0 comments posted 19yrs posted by mottoblatto

TI TFP410 DVI transmitter help?

I am trying to use I2C to configure TI TFP410 DVI transmitter. I put differential clock input and VSYNC/HSYNC with the...
5 comments posted 19yrs
posted by ssc3k
5 comments posted 19yrs posted by ssc3k

Xilinx Spartan 3 Configuration

Hi i have 3 X Spartan 3 to configure i followed the Master Serial configuration from the application note, but the samp...
0 comments posted 19yrs
posted by yy7d6
0 comments posted 19yrs posted by yy7d6

How to save preferences of modelsim

Hi, The default font of the source window in Modelsim III 6.1e is too large. Although it is changed after I set it in "...
0 comments posted 19yrs
posted by rxjwg98
0 comments posted 19yrs posted by rxjwg98