1. Home
  2. Field-Programmable Gate Arrays
  3. RTL deisgn for Blocking and Nonblocking

RTL deisgn for Blocking and Nonblocking

Hi,

Please clarify me about blocking and nonblocking statement difference in RTL design.

CODE1: always@(X or Y or Z) begin Q1 = X & Y; Q2 = Q1 & Z; end

CODE2: always@(X or Y or Z) begin Q1

Reply to
himassk
Loading thread data ...

himassk -

Do some Googling. This topic is well covered in many papers that are available on the web.

As you read, remember this rule of thumb: For synchronous logic, use non-blocking. For combinatorial logic, use blocking.

Also - why are you posting this Verilog specific question to the FPGA newsgroup?

John Providenza

himassk wrote:

Reply to
johnp

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.