I have a setup that is passing behavioral sim but not timing sim. The basic setup is as follows. I have a 100 MHz clock input to a Virtex 4 FPGA (ML401 board - LX25 -10). It goes through a global buffer and connects to a DCM. The DCM multiplies this clock by 3 and outputs that on CLKFX. That output is connected to a buffer that, in turn, connects to another DCM input. The second DCM outputs on CLK0, CLK90, CLK180, and CLK270. The first DCM does NOT have a feedback source. I know there are caveats about doing this, but the only warnings I have had from Xilinx are in regards to the output phases of the DCM not having a known phase relationship with respect to the input clock. That doesn't matter to me.
I have the CLK0 output of the second DCM connected to a global buffer. Then the global buffer is connected to a BUFR. The output of the BUFR drives 24 FF's. There is one LUT in the design. Basically serial data is clocked into 2 banks of 8 FF's. The other 8 FF's implement a 'wrap-around' shifter. When the last bit of that shifter is a one, the enable to the first bank of 8 FF's is turned off and the enable to the second set of 8 FF's is turned on. That way I get two 8-bit shift registers ping-ponging data captured at the clock rate divided by 8. Eventually I will move the data at the divided clock speed...basically deserailizing the input data. I have only built the CLK0 logic so the other clocks are optimized out.
I have run a post-place-and-route sim. At an input clock of 100 MHz to the first DCM, the output clocks from the second DCM should all be 300 MHz. This is fine. The problem is with the BUFR. The CE is 1'b1, the CLR is a 1'b1 that goes low when the second DCM locks. This should ensure that a valid clock is input to the BUFR, and I would expect the BUFR to just forward the input clock. I am using the divider value of the BUFR set to '1'. However, when running the sim at this speed, the 'I' input to the buffer is '0' and then goes to a steady '1'. There is NO CLOCK signal at the input!! I can slow the sim input clock by half and everything works OK. Why would I not see the clock at full speed? Is there a SIMPRIM constraint that I do not know about? 300 MHz does not seem unreasonable. I don't know if there is some DCM/BUFG/BUFR connection I am doing wrong either.
Thanks for any help...or thanks for just reading this!