Hello,
in my design for a Spartan 3 4000 FG676-4 I have included a DCM that =
synthesizes a clock of 20 MHz out of external 100 MHz. I get the followi= ng =
warning message from bitgen, version 7.1.04i -H.42
Running DRC. INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis =
performance with the CLKFX and CLKFX180 outputs of the DCM comp dcm_1/DCM_INST/dcm_1/DCM_INST, consult the device Interactive Data =
Sheet. DRC detected 0 errors and 0 warnings. Creating bit map... WARNING:Bitgen:200 - CLKFX period 50000 ps is greater than maximum of =
41700 ps.
The minimum output frequency that is allowed according to the Spartan3 =
Datasheet and the DCM datasheet for Spartan3 are 18 MHz. Why do I get th= is =
warning? 41700 ps are approx. 24 MHz.
I use the DCM as follows.
dcm_1 : dcm_100_20 PORT MAP ( CLKIN_IN =3D> CLK, RST_IN =3D> reset, CLKFX_OUT =3D> clk_20, CLKIN_IBUFG_OUT =3D> clk_100, CLK0_OUT =3D> OPEN, LOCKED_OUT =3D> dcm_locked);
Thanks for your help or some hints in advance. Ingmar Seifert