Field-Programmable Gate Arrays

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ANNC: SPI4.2 in low-cost 90nm FPGA webcast

Lattice is holding a webcast today, Wednesday, September 6 "Low-Cost FPGA Supports Full Rate SPI4.2 Implementation." Th...
0 comments posted 19yrs
posted by bart.borosky
0 comments posted 19yrs posted by bart.borosky

NON-CLK pins failed to route using a CLK template

I am designing a frame grabber .The frame input is expeted at a very slow rate of 10mbps. I have 4 state machine strutu...
5 comments posted 19yrs
posted by dhruvakshad
5 comments posted 19yrs posted by dhruvakshad

How to bound a Cores generated output in Modelsim

Hi, I am learning Xilinx ISE Webpack 8.2. There is an example watchvhd.ise # -- Compiling entity testbench # -- Compili...
7 comments posted 19yrs
posted by rxjwg98
7 comments posted 19yrs posted by rxjwg98

Global constants definition problem

Hi, Help is needed. I have some global constants shared among several modules, so I set up a file to define a global pa...
9 comments posted 19yrs
posted by wtxwtx
9 comments posted 19yrs posted by wtxwtx

RLOC problems

I'm playing around a bit with RLOC and I'm getting some weird results. My top level file has these instantiations in it...
1 comments posted 19yrs
posted by ehliar
1 comments posted 19yrs posted by ehliar

Packages for ORCAD

Hello. Do anybody have ORCAD library for Xilinx xc3s1500 in FG320 package and TI TMS320C6713BGDP300? Thanks, Dmitry.
1 comments posted 19yrs
posted by in_spb3
1 comments posted 19yrs posted by in_spb3

exporting an image with quartus 2 web edition

Hi there I'm trying to export a waveform from the quartus 2 web edition. In the quartus 2 help, there's a nice explanat...
1 comments posted 19yrs
posted by tthurnherr
1 comments posted 19yrs posted by tthurnherr

Virtex4 FPGA minimum power

A Virtex4 FPGA is mounted on a board which has a sleep mode to conserve battery power during periods of inactivity. Is...
2 comments posted 19yrs
posted by pomerado
2 comments posted 19yrs posted by pomerado

Serial I/O Question

I need to recover data from a serial LVDS I/O stream running at over 300 MHz. A reference 26 MHz clock is provided by t...
7 comments posted 19yrs
posted by mottoblatto
7 comments posted 19yrs posted by mottoblatto

LUT Blocks?

hi how do i enter the 16 bit number of a 4 input 1 output lut to get a compact block design file for easy use?? is this...
1 comments posted 19yrs
posted by jackokring
1 comments posted 19yrs posted by jackokring

FPGA multiplier

from the Xilinx Virtex4 spec: =B7 XtremeDSP=99 Slice - 18x18, two's complement, signed Multiplier - Optional pipeline s...
10 comments posted 19yrs
posted by sutejok
10 comments posted 19yrs posted by sutejok

Exploring Quartus' Messages and Warnings

During the synthesis process, Quartus reports "Ignoring invalid Fast-IO-Timing Assignments" which I am not able to disc...
9 comments posted 19yrs
posted by fpgaengineerfrankfurt
9 comments posted 19yrs posted by fpgaengineerfrankfurt

Raggedstone1 PCI Shipping Build

Finally at last for all Raggedstone1 owners that have been asking there is now a new PCI shipping build available on ou...
0 comments posted 19yrs
posted by removethisthenleavejea
0 comments posted 19yrs posted by removethisthenleavejea