Altera CPLD 7128S heating up

Sep 07, 2006 6 Replies

Hi,



I work on a board with an Altera 7128S part (5V quite old but still used ...). It seems the part is most of the time working just fine but depending on when it is powered on it overheats a lot and does not seem to be well configured : an input acts as an output, and the component is not working fine at all. Does anyone havea clue as to what could be going wrong ? It does not happen all the time.



Thanks,



JF


This sounds suspiciously like latch-up caused by a power sequencing problem; typically, +5V or some other power rail applied to a device's input before the device itself has been powered-up. This can easily happen if you have voltage level-shifters on the CPLD's input, taking an external 12V or 24V signal and dropping it to 5V for the device. It can also happen if you have multiple interconnected PCBs with separate power to each.

The problem can often be solved by adding current limiting resistors in series with each susceptible input. Keep the worst-case input current below about 1mA and you should be safe. These resistors will restrict the input bandwidth, but otherwise should cause no trouble.

Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.

Does this part have JTAG, and if so does it have the TRST pin? I had a lot of trouble with an Actel ProAsic device and the JTAG boundry scan. I finally had to tie the TRST pin low to keep it out of the boundry scan mode. Also check that your rise time on your VCC is within limits for the part.

Does this part have JTAG, and if so does it have the TRST pin? I had a lot of trouble with an Actel ProAsic device and the JTAG boundry scan. I finally had to tie the TRST pin low to keep it out of the boundry scan mode. Also check that your rise time on your VCC is within limits for the part.

I read some errata from Altera's site about a MAX3k family. I had a MAX3128 do something like what you're experiencing -- it was a power sequencing issue.

As someone else suggested, check the power sequence and perhaps avoid driving the 7128S's inputs if it's not fully up yet.

John.

You get this behaviour too when the TCK pin is not properly pulled up (or down, whichever). But, as most suggest, this smells of a power-sequencing issue.

Best regards,

Ben

No, it *smells* of hot epoxy...

-- Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK snipped-for-privacy@MYCOMPANY.com

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