Field-Programmable Gate Arrays

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System Generator Bug

Hi, I found a bug inthe System Generator 8.2i. Every time when I click on the DSP block under Xilinx Reference Blockset...
0 comments posted 20yrs
posted by kuan.zhou
0 comments posted 20yrs posted by kuan.zhou

http://www.srisc.com ?

Ok, so a link to these people came across my mail box today. and its supposedly a Open Source 64bit sparc core.. Anyone...
6 comments posted 20yrs
posted by ziggy
6 comments posted 20yrs posted by ziggy

Parallel P&R

Anyone know if the P&R tools are multi-threaded ? And, if they're not, whether there are any plans to make them so ? Ev...
2 comments posted 20yrs
posted by google
2 comments posted 20yrs posted by google

upgrading firmware on stratix 2 without NIOS IDE

I am writing a firmware application that allows the verilog hardware on the stratix 2 board to communicate via rs232 to...
5 comments posted 20yrs
posted by jeffjohnsonce
5 comments posted 20yrs posted by jeffjohnsonce

Re: microblaze lwip

> As linker options i use : -lxilkernel -llwip4 > > when i build the projet i get the following error message: > > Buil...
2 comments posted 20yrs
posted by alan
2 comments posted 20yrs posted by alan

USB programming cables

So, having bought the V4FX-12 kit from NuHorizons, it arrived with a parallel-port JTAG cable. Normally I'd be just *fi...
9 comments posted 20yrs
posted by news
9 comments posted 20yrs posted by news

Fusion

Does anyone know if ANY of the Actel fusion devices are available for purchase? -Eli
4 comments posted 20yrs
posted by emh203
4 comments posted 20yrs posted by emh203

problems with IOSTANDARD

Hi to all, I'm trying to set the output voltage level of a Virtex 2 pro using the IOSTANDARD constraint, but it doesn't...
10 comments posted 20yrs
posted by mgeisse
10 comments posted 20yrs posted by mgeisse

Xilinx Connect custom peripheral to PPC

Hi everyone, after I have imported my custom peripheral into XPS 8.2i, I added the Design to my System (XC2VP30). The c...
1 comments posted 20yrs
posted by peter.kampmann
1 comments posted 20yrs posted by peter.kampmann

net skew

Hi I have a design that I am having trouble routing. When I look at the cloc signals the net skew for one is about 0.8n...
2 comments posted 20yrs
posted by maxascent
2 comments posted 20yrs posted by maxascent

Critcal path in XILINX ISE (XST)

Hi, Can you please tell me where I can see the critical path in Xilinx ISE tool? I am using XST as synthesis tool. Regar...
1 comments posted 20yrs
posted by makarand.deshmukh
1 comments posted 20yrs posted by makarand.deshmukh

Unwanted clock on output pin....

I am using the ML401 board to build up some test logic. The 100MHz XO on the baord is fed into a DCM via a global buffe...
3 comments posted 20yrs
posted by mottoblatto
3 comments posted 20yrs posted by mottoblatto

Spartan3 driving mosfets

I've got some DACs that I'd like to switch gain ranges on, and it turns out I can do it nicely using a single 2N7002 (s...
15 comments posted 20yrs
posted by jjlarkin
15 comments posted 20yrs posted by jjlarkin