I am designing a four-bit shift register using four 4 - 1 MUXes and four D Flip-Flops. This is to be connected in a schematic to a push-button debounce switch and a clock divider.
My shift register works when i test-bench the verilog, but when coonected to the other components in the schematic, the shift register doesn't select; The output is always the default value in the MUX's case statement. Can anyone help???? This was done in xilinx ise 6.3i. The code below is the flip flop, the mux, the structural verilog of the shift reg, a switch debounce and a clock divider
module dFlipFlop(clk, reset, d, q); //Port List input clk; input reset; input d; output q; reg q; //Redeclaration of output always@(posedge clk or posedge reset)begin if(reset == 1'b1)begin q = 1'b0; end else begin q = d; end end endmodule
module fourToOneMux(i0, i1, i2, i3, sel, y); input i0, i1, i2, i3; input [1:0] sel; output y; reg y; always@(i0 or i1 or i2 or i3 or sel)begin case({sel}) 2'b00: y = i0; 2'b01: y = i1; 2'b10: y = i2; 2'b11: y = i3; default: y = 2'hx;//garbage endcase end endmodule
module shiftRegisterFourBit(clk,reset,si,m0, m1,d,q); input clk, reset; input si, m0, m1; input [3:0] d; output [3:0] q; wire[3:0] q; wire w0, w1, w2, w3;
fourToOneMux mux0(q[1], si, d[0], q[0],{m1, m0}, w0); fourToOneMux mux1(q[2], q[0], d[1], q[1],{m1, m0}, w1); fourToOneMux mux2(q[3], q[1], d[2], q[2],{m1, m0}, w2); fourToOneMux mux3(si, q[2], d[3], q[3], {m1, m0}, w3);
dFlipFlop dff0(clk, reset, w0, q[0]); dFlipFlop dff1(clk, reset, w1, q[1]); dFlipFlop dff2(clk, reset, w2, q[2]); dFlipFlop dff3(clk, reset, w3, q[3]);
endmodule
module switchDebounce(clk, reset, din, dout); input clk, reset, din; output dout; wire dout; reg q3, q2, q1, q0;
always@(posedge clk or posedge reset) if(reset == 1'b1) {q3, q2, q1, q0} = 25000)begin clk_out = ~clk_out;
end end endmodule