Hi to all,
I'm trying to set the output voltage level of a Virtex 2 pro using the IOSTANDARD constraint, but it doesn't work.
More exactly, I'm using the XUP Virtex-II Pro Development System (an evaluation board) by Xilinx. For an application, I need the FPGA to output 3.3 V signals on the left low-speed expansion connector. I have tried to achieve this by placing the following lines in my UCF file (using one of the signals as an example):
NET "camera_sio_d" LOC = "U3"; NET "camera_sio_d" IOSTANDARD = LVTTL;
However, the FPGA outputs 2.5 V for digital 1 (0 V for digital 0), measured with no load on the signal. I have tried different values for IOSTANDARD as an experiment (LVTTL, LVCMOS33, LVCMOS15, and omitting the constaint altogether), but nothing happens - I still get 2.5 V. The scope is fast enough, and by tweaking the timing a bit I can say that these voltage levels are stable (no capacity being charged anymore). The voltage supply for the whole board also seems to be okay. Note that even LVCMOS15 (which should give me 1.5 V) doesn't work, so I don't think it's an electrical problem.
To avoid problems with banking rules for the pins, I have set all pins on the relevant bank to the levels described above. The implementation tools do complain if the IOSTANDARD of different pins on the same bank mismatch, so I think I'm not doing this anymore. To be sure, I have looked at the pad report, and also viewd the placed and routed configuration in the FPGA editor. Both tell me that the IOSTANDARD is indeed set to the value I want. Still I get 2.5 V when programming the real FPGA.
Thanks in advance for any ideas.