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Unwanted clock on output pin....

I am using the ML401 board to build up some test logic. The 100MHz XO on the baord is fed into a DCM via a global buffer. I am using the FX output (x3) to bump the clock up to 300MHz. There is no feedback source on this DCM b/c I don't care about its input/output phase relationship. That FX output is fed to another DCM. The CLK0, CLK90, CLK180, CLK270, and CLKDIV outputs are all used.

I am using a data generator to input an LVDS signal. The two signals (data_p and data_n) are fed into the FPGA and connected to an instantiated differential buffer with an LVDS_25 attibute. The output of the buffer is fed to both an external IO and internal logic. I just want to check to make sure the LVDS signal is being transmitted and buffered correctly.

I am scoping the output IO (buffered LVDS - single-ended signal at this point) and see some odd behavior. With the LVDS signal ON, the output of the pin looks good. It is the single-ended data I would expect. However, if I turn the data generator off, I get a 300 MHz clock on the output. It is at the IO voltage too - 2.5V...and clean! Now, I can turn the OUTPUT channels of the data generator off. That removes the DC bias on the data_p and data_n signals. The output on the IO pin at that point is garbage...no signal, but it is ugly...not 0 output.

If I reset the board...really just resets the DCM and internal logic of the FPGA, the output IO is a 100MHz clock! Remember, this is with the data generator output channels OFF. If I turn them ON (channles are DC biased but no activity on them) and THEN reset the board, I will get the 300MHz clock output. The weird thing is, is that I can HOLD the reset to the board and the 300MHz clock never goes away! I would think that the reset to the DCM's would disable all clock signals. I have checked the data generator to make sure that it wasn't introducing a rogue clock. It isn't. I have moved its output frequency around and never seen it on the output.

I really haven't looked into this much, but wanted to throw it out here to see if I am missing something obvious.

Thanks.

Reply to
motty
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Reply to
Peter Alfke

Peter Alfke schrieb:

Hi Peter,

thanks for the explanation - I was struggling with something similar, I was experimenting on on-chip oscillators, so I also tried a IOB oscillator with LVDS the funny thing is that if an LVDS output is driven, but the traces are short circuit outside the chip the input LVDS buffer still receives the signal as if ther is no short circuit at all!

ah this was actually an attempt to use LVDS as short circuit tester, eg tester that senses short circuit but not silicon mounted on boards, it requires voltage below 0.5V so LVDS seems ok, but -- as the input readback is so sensitive it will see the external short circuit not short enough and still sense the signal.

if you have LVDS based ring oscillator then making a short circuit on the LVDS pins (no matter how close to the chip!) will not make the oscillator stop, the frequency if I so recall just goes a bit higher with outputs shorted. This sounds a bit strange as the LVDS outputs should not be abel to drive over the treshold with output shorted, but so it is as of experiments.

failed attempt - but was fun experiment

Antti

Reply to
Antti

Thanks Peter.

My only problem is that I can reset (hold down the reset button!) the whole thing and STILL get a 300 MHz clock on the output. Asserting reset should reset the DCM that bumps the 100 MHz to 300 MHz. Actually, in reset, there should be no clocks in the FPGA except for the input 100 MHz clock from the XO. According to DCM documentation, the reset will force all outputs to 0.

I have traced the rest signal to the DCm in the technology schematic, the floorplanner, and the FPGA editor to cover all bases. It is connected properly.

thanks again!

Reply to
motty

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