Field-Programmable Gate Arrays

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Virtex-5 LXT orderable?

http://www.sierraic.com/pnresults.asp?part=XC5VLX50T1FF1136CES there is status "available" - and full order code as wel...
5 comments posted 20yrs
posted by Antti.Lukats
5 comments posted 20yrs posted by Antti.Lukats

[ISE8.2] DIFF_TERM and unused pin

Hey, I have 2 LVDS clock signals and both are terminated with the DIFF_TERM attribute on the LVDS25 input buffer IBUFGD...
7 comments posted 20yrs
posted by tim.verstraete
7 comments posted 20yrs posted by tim.verstraete

Xilinx documentation typos

Hello, Don't know if this is the right place to report this, but... While reading some xilinx docs I came across the fo...
27 comments posted 20yrs
posted by jbnote
27 comments posted 20yrs posted by jbnote

Spartan-3/3E Board

Hi all, I looking for a Spartan-3/3E based board with the following features (other features are also welcome): - 8-way...
1 comments posted 20yrs
posted by taileb.mehdi
1 comments posted 20yrs posted by taileb.mehdi

Last ISE version that supports XC95xxXL ?

Hi can someone suggest what version of ISE would be best candidate not to fail on XC95xxXL fitting? ISE 8.2SP3 fails ba...
8 comments posted 20yrs
posted by Antti.Lukats
8 comments posted 20yrs posted by Antti.Lukats

OT: Internships?

Hi guys, I am currently in the process of looking for an internship position that will potentially start in May and end...
11 comments posted 20yrs
posted by x86asm
11 comments posted 20yrs posted by x86asm

Which Xilinx FPGA/board?

Dear Comrades, I am trying to implement a large design on a Xilnx FPGA (over 500,000 gates). Spartan 3E seems like the...
2 comments posted 20yrs
posted by rohit.nadig
2 comments posted 20yrs posted by rohit.nadig

Glitches in post-layout (PAR) simulation

Hey all, I've managed to synthesize a particular DSP core on Actel's fusion FPGA. I'm using this as a benchmark to asse...
14 comments posted 20yrs
posted by mloulah
14 comments posted 20yrs posted by mloulah

VirTex 4 mini Module

Has anyone her had experience with this Board? I really like these small modules.... Wish there were more out there. I...
1 comments posted 20yrs
posted by emh203
1 comments posted 20yrs posted by emh203

Coregen GMII embedded ethernet MAC

I have been trying to implement Virtex-4 Tri-Mode Embedded Ethernet MAC Wrapper v4.3(GMII) from coregen in ISE. All gui...
1 comments posted 20yrs
posted by RUNE_dahl
1 comments posted 20yrs posted by RUNE_dahl

ISO plb_temac driver for linux 2.4

Does anyone have the source tree for the plb_temac (ver 2.00) driver under linux 2.4? I am using the plb_temac on the Xi...
0 comments posted 20yrs
posted by rdcorle
0 comments posted 20yrs posted by rdcorle

power up delay in fpga

i would like to know how much time it would take for the spartan 3 fpga to get configured after power on
1 comments posted 20yrs
posted by reshmi3083
1 comments posted 20yrs posted by reshmi3083

Partial Reconfiguration using XUPV2P

Hi, I'm exploring partial reconfiguration and I'm trying to find an example design sucessfully implemented using the XU...
0 comments posted 20yrs
posted by dpmontminy
0 comments posted 20yrs posted by dpmontminy