Field-Programmable Gate Arrays

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Am I blind or? (Virtex-4 issues)

Hi, Virtex-4 has many new things, one of them is access to CCLK as output after configuration. CCLK control is required...
6 comments posted 20yrs
posted by Antti.Lukats
6 comments posted 20yrs posted by Antti.Lukats

EDK speed optimisation

in an EDK project, is it possible (as with ISE) to verify vhdl syntax of one file, before a long long make that abort c...
2 comments posted 20yrs
posted by rponsard
2 comments posted 20yrs posted by rponsard

VGA timing

Hi everbody, I wanna implement VGA core at 1024x768x75Hz (15" LCD Monitor) on Spartan3E starter kit. I have got a few q...
9 comments posted 20yrs
posted by icegray
9 comments posted 20yrs posted by icegray

rocketIO in custom mode

May I use rocketIO (Virtex2PRO) in custom mode for serialize/deserialize STM-1 (155.52 Mb) ?
2 comments posted 20yrs
posted by axalay
2 comments posted 20yrs posted by axalay

Cyclone PLL

Hi all, I'm new in this field. Please guide me how can I proceed to implement the cyclone altpll megafunction in my own...
1 comments posted 20yrs
posted by kkay.scorpz
1 comments posted 20yrs posted by kkay.scorpz

spartan 3E starter kit and JOP

does anyone port JOP (www.jopdesign.com) to the spartan 3E starter kit (xc3s500e) ? there is an implementation for the...
0 comments posted 20yrs
posted by rponsard
0 comments posted 20yrs posted by rponsard

Functional Languages in Hardware

Are there any functional languages that can be compiled to hardware at the same or greater level of abstraction than la...
8 comments posted 20yrs
posted by shidan
8 comments posted 20yrs posted by shidan

OT: sun vs xilinx

Sorry for the OT post... but the curiosity... (kill the cat...) Is Sun acquiring Xilinx ? http://www.xilinx.com/favicon....
0 comments posted 20yrs
posted by sdroamt
0 comments posted 20yrs posted by sdroamt

TIG Being Ignored?

I've been performing post-map static timing analysis and have noticed that my TIG UCF constraint is being ignored for s...
5 comments posted 20yrs
posted by killerhertz
5 comments posted 20yrs posted by killerhertz

Virtex 4 RAMB16 Clock: optional inverter missing

Hello, The RAMB16 component has much less clock-to-out time when using the optional output register. However, I need va...
4 comments posted 20yrs
posted by leischni
4 comments posted 20yrs posted by leischni

Release Status of Spartan3E

Hello, a look at the Xilinx "online" shop or other Xilinx sources shows that the Product line of Spartan 3E still shows...
4 comments posted 20yrs
posted by bon
4 comments posted 20yrs posted by bon

Q on sync resets (yes, again!)

Hi, With all this talk of sync resets, I was curious: 1. If you apply reset async and de-assert sync, does this signal...
0 comments posted 20yrs
posted by bogus
0 comments posted 20yrs posted by bogus

ARMv6 ISA doc required plz help

Hi , I need either the ARMv6 ISA or the ARMv7-A ISA doc. Please help Thanks, Vits
2 comments posted 20yrs
posted by vittal.patil
2 comments posted 20yrs posted by vittal.patil