Hey,
I have 2 LVDS clock signals and both are terminated with the DIFF_TERM attribute on the LVDS25 input buffer IBUFGDS but i only use 1 of them ... now i want both buffers to stay in my design and not optimized away. Is there a constraint that i can place on that buffer? i guess that it should be a UCF constraint since when i look into the RTL viewer of planahead and ISE i still see the buffer.
I know that there is an option in NGBuild -u which keeps the unused logic, but i do not want to use it just for that 1 buffer ...
thanks in advance,
kind regards,
tim
p.s. i'm using ISE8.2SP2 and a V4SX55-FF1148C