I've managed to synthesize a particular DSP core on Actel's fusion FPGA. I'm using this as a benchmark to assess their suitability for further integration. I'm a bit new when it comes to Actel. Anyway, it seems that when running post-PAR simulation I end up having a periodic pattern of 1ns wide glitches in my output signal every like 4 or slightly less sampling periods. My design is fully synchronous. I have no clue whatsoever about the source of the glitches. I even tried to leave some temporal margin before doing the final output assignment (for thigs to settle down) but it didn't work. Would really appreciate it if anybody can give me an insight on possible problematic sources. I'm yet to run my design in hardware as I'm still waiting for the kit to arrive.
Thanks in advance guys.