Hi,
i try to implement the Aurora Example Design to a Virtex-4FX20 device on the ML405 Evaluation Board from Xilinx. I generate the core with the "Core Generator" and with the following settings:
Aurora Lanes: 1 Lane width: 2 bytes Interface: Framing Duplex-Mode Native Flow Control: Immediate Mode User Flow Control
Line Rate: 2.5 Gbps REF-CLK: 125 MHz
Col. 0 Clock: REF_CLK_1 MGT 105B Position: Y0X0
On the ML405 Board the TX and RX Pins of the MGT 105B are connected together so i have a external loopback. The Example Design includes a frame generator and a frame checker. To run the Aurora Example Design on the Virtex device i edit the aurora_sample.ucf file to the correct io-pins for the ML405 Board. I believe thats all i have to do, but it doesn't work. The CHANNEL_UP signal doesn't assert but there is no error indicated. I don't know what went wrong.
Can someone help me?????????