Field-Programmable Gate Arrays

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Meeting Timing Constraint

A design is built to work at 50MHz, but the deisgn when tested works only at 48MHz. What should we do to make the desig...
8 comments posted 19yrs
posted by hpsham
8 comments posted 19yrs posted by hpsham

Learner

Hi all, I am learner in FPGA design. You could send any tutorials or some information regarding this. Thamks all.
1 comments posted 19yrs
posted by thota.raghavendrarao
1 comments posted 19yrs posted by thota.raghavendrarao

generic ROM memory help

Hi. I am trying to write generic VHDL code of ROM (read only memory). Values that shoud be writen in the memory need to...
0 comments posted 19yrs
posted by Zorjak
0 comments posted 19yrs posted by Zorjak

Executing PPC code from external flash memory

I have a EDk based design with 8 MB of external flash memory on PLB via the plb_emc core. This is for a Virtex II Pro u...
3 comments posted 19yrs
posted by sgfallows
3 comments posted 19yrs posted by sgfallows

FIR filter fpga help

Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask fo help. I have two (X and Y) channels and their fr...
6 comments posted 19yrs
posted by ckh827
6 comments posted 19yrs posted by ckh827

Cheapest FPGA board to study VHDL on

Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) Whats the cheapest board to study VHDL on? Ide...
27 comments posted 19yrs
posted by samiamSPAMTHIS
27 comments posted 19yrs posted by samiamSPAMTHIS

EDIF netlist timing simulation

Hi, I am having a problem with simulation of EDIF netlist file. I have generated EDIF file using leonardospectrum synth...
3 comments posted 19yrs
posted by makarand.deshmukh
3 comments posted 19yrs posted by makarand.deshmukh

from LUT contents to boolean equation

Hello, I'd like to know if there is any documentation on the (presumably normal) form of the LUT boolean equations as u...
3 comments posted 19yrs
posted by jbnote
3 comments posted 19yrs posted by jbnote

New IP with EDK : how connect external NET ?

I am creating my own test IP and can't find the proper way to generate external NET connection with logic using graphic...
3 comments posted 19yrs
posted by rponsard
3 comments posted 19yrs posted by rponsard

how to implement integrator?

Hello all, I want to implement integrator using vhdl, all xilinx logic core, is it available or anyone worked on this to...
6 comments posted 19yrs
posted by jaywant.kolhe
6 comments posted 19yrs posted by jaywant.kolhe

64 bit division compensate NCO

Hi everyone, I'm currently using a vitex-II pro FPGA, I've implemented an NCO frequency generator, which is supplied wi...
9 comments posted 19yrs
posted by luca_grossi
9 comments posted 19yrs posted by luca_grossi

8B/10B vs. Start/Stop for SERDES

I'm doing a new design with a SERDES at 1.6Gbps. For cost reasons, I'm using an FPGA without serial IO, so I'm looking...
2 comments posted 19yrs
posted by boyscout
2 comments posted 19yrs posted by boyscout

Xilinx ISE UCF question

Hey all I saw this on an example design (on Xilinx ISE): NET clkb PERIOD = 25ns; NET "clkb" LOC = A16; what does it mea...
1 comments posted 19yrs
posted by sutejok
1 comments posted 19yrs posted by sutejok

OpenCores.org's I2C: Clock Stretching Support

Hi, I'm currently working with the I2C core supplied by OpenCores.org. I have successfully got the design to work in an...
1 comments posted 19yrs
posted by markus_1401
1 comments posted 19yrs posted by markus_1401