Latest threads in Field-Programmable Gate Arrays

Problema when upgrading from Xilinx 8.1 to Xilinx 8.2

This is not strictly a call for help, it is more of a warning to everyone. Yesterday, I tried to upgrade from ISE/EDK 8...

13 20yrs

me_zara

13 20yrs me_zara

Meeting Timing Constraint

A design is built to work at 50MHz, but the deisgn when tested works only at 48MHz. What should we do to make the desig...

8 20yrs

hpsham

8 20yrs hpsham

Learner

Hi all, I am learner in FPGA design. You could send any tutorials or some information regarding this. Thamks all.

1 20yrs

thota.raghavendrarao

1 20yrs thota.raghavendrarao

DDR access for multiple procs on a ML310 (Virtex-II Pro)

Does anyone know if it is possible to have mutltiple processors be able to access the DDR memory in an ML310 board(Virt...

1 20yrs

HEEEY.STEVE

1 20yrs HEEEY.STEVE

generic ROM memory help

Hi. I am trying to write generic VHDL code of ROM (read only memory). Values that shoud be writen in the memory need to...

0 20yrs

Zorjak

0 20yrs Zorjak

Executing PPC code from external flash memory

I have a EDk based design with 8 MB of external flash memory on PLB via the plb_emc core. This is for a Virtex II Pro u...

3 20yrs

sgfallows

3 20yrs sgfallows

FIR filter fpga help

Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask fo help. I have two (X and Y) channels and their fr...

6 20yrs

ckh827

6 20yrs ckh827

Cheapest FPGA board to study VHDL on

Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) Whats the cheapest board to study VHDL on? Ide...

27 20yrs

samiamSPAMTHIS

27 20yrs samiamSPAMTHIS

EDIF netlist timing simulation

Hi, I am having a problem with simulation of EDIF netlist file. I have generated EDIF file using leonardospectrum synth...

3 20yrs

makarand.deshmukh

3 20yrs makarand.deshmukh

from LUT contents to boolean equation

Hello, I'd like to know if there is any documentation on the (presumably normal) form of the LUT boolean equations as u...

3 20yrs

jbnote

3 20yrs jbnote

New IP with EDK : how connect external NET ?

I am creating my own test IP and can't find the proper way to generate external NET connection with logic using graphic...

3 20yrs

rponsard

3 20yrs rponsard

how to implement integrator?

Hello all, I want to implement integrator using vhdl, all xilinx logic core, is it available or anyone worked on this to...

6 20yrs

jaywant.kolhe

6 20yrs jaywant.kolhe

64 bit division compensate NCO

Hi everyone, I'm currently using a vitex-II pro FPGA, I've implemented an NCO frequency generator, which is supplied wi...

9 20yrs

luca_grossi

9 20yrs luca_grossi

8B/10B vs. Start/Stop for SERDES

I'm doing a new design with a SERDES at 1.6Gbps. For cost reasons, I'm using an FPGA without serial IO, so I'm looking...

2 20yrs

boyscout

2 20yrs boyscout

Xilinx ISE UCF question

Hey all I saw this on an example design (on Xilinx ISE): NET clkb PERIOD = 25ns; NET "clkb" LOC = A16; what does it mea...

1 20yrs

sutejok

1 20yrs sutejok

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