Field-Programmable Gate Arrays

playing with ML501, first impressions

Virtex-5 Evaluation board ML501 Testing ============================= Preloaded designs: All CompactFlash demos worked...

0 comments posted 19yrs

posted by Antti.Lukats

0 comments posted 19yrs posted by Antti.Lukats

ANNC: Open Source, Free 32-bit soft processor webcast

Lattice is holding a webcast tomorrow Wednesday, October 18, "Embedded Design with LatticeMico32 Open, Free 32-bit Soft...

5 comments posted 19yrs

posted by bart.borosky

5 comments posted 19yrs posted by bart.borosky

Getting info from XST, Homework Question, netlist, reports, etc...

I am finally at the synthesis portion of the course. My code "compiles", simulates, sythesisizes and implements correct...

2 comments posted 19yrs

posted by kyle.hable

2 comments posted 19yrs posted by kyle.hable

Need info: Altera dual-port & fifo act different (func vs VITAL)

I have a number of Dual-Port Rams and FIFOs that I've implemented with Quartus II 6.0 sp#1, targeting a Stratix II devi...

2 comments posted 19yrs

posted by rjmyers

2 comments posted 19yrs posted by rjmyers

Picoblaze + Blockram + Data3Mem = help needed

Hi folks, I am just trying my first steps with the picoblaze. And I feel alone with some questions. My situation [to av...

1 comments posted 19yrs

posted by hachti

1 comments posted 19yrs posted by hachti

Xilinx DCT reference design

I am a student working on a simple MPEG-2 encoder and want to use the Xilinx DCT in Application note 610. The DCT has 8...

0 comments posted 19yrs

posted by anders.rustad

0 comments posted 19yrs posted by anders.rustad

xilinx power pc & microblaze

Hi, Can anyone point me out anything that I could read about using both PowerPCs on Virtex 2 Pro. Or using more than 1...

1 comments posted 19yrs

posted by eascheiber

1 comments posted 19yrs posted by eascheiber

Block Memory Generator: Wrong data in BRAM after initialization with *.ceo File

Hi, i'm using Block Memory Generator 2.1 for a 16bit * 1024 RAM implemented in virtex4 BRAM and want to initialize the...

4 comments posted 19yrs

posted by ben.schuffenhauer

4 comments posted 19yrs posted by ben.schuffenhauer

Newbie : Please give me an idea about programming an FPGA

Hi everyone, I am new to the FPGA, and would like to know more about how we can program an FPGA to do a complex task. P...

7 comments posted 19yrs

posted by leeaby

7 comments posted 19yrs posted by leeaby

mapping memory to fpga

hiiiiiii, I am designing a switch controller to be implemented on FPGA,i need to map memory blocks to FPGA,are there an...

1 comments posted 19yrs

posted by ashu_19_1980

1 comments posted 19yrs posted by ashu_19_1980

GTKWave 3.0.13 for win32

Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.0.13 now: http://www.dspia.com/gtkwave.html

0 comments posted 19yrs

posted by kal*

0 comments posted 19yrs posted by kal*

FPGA + GSM cores

Does anyone have any good links to groups/companies working on GSM or CDMA IP cores? Or maybe something like a GSM SDR?...

3 comments posted 19yrs

posted by karrelsj

3 comments posted 19yrs posted by karrelsj

Missing Xilinx EDK Temac example

On Xilinx's website page: http://www.xilinx.com/ise/embedded/edk_examples.htm There are 2 LWIP EDK example designs, one...

0 comments posted 19yrs

posted by paul.tobias

0 comments posted 19yrs posted by paul.tobias

Re: ADC (LTC1407a) on Xilinx Spartan 3E starter kit

I found the problems come from other SPI devices on board, which should be disabled but I didn't. "Ju, Jian" ?ÈëÏû?ÐÂÎÅ...

0 comments posted 19yrs

posted by eejju

0 comments posted 19yrs posted by eejju

ISE On Intel Mac

Is anyone running ISE on an Intel based Macintosh? I'm considering a MacPro with dual Core 2 Duo processors, running ISE...

2 comments posted 19yrs

posted by user

2 comments posted 19yrs posted by user