how to implement integrator?

Hello all, I want to implement integrator using vhdl, all xilinx logic core, is it available or anyone worked on this topic?

Jaywant

Reply to
Jai
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What do you mean by "integrator"? do you need to integrate over time, over frequency?

Al

Jai wrote:

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Alessandro Basili
CERN, PH/UGC
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Al

Reply to
Jai

It's very easy...

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity integrator is port ( clock : in std_logic; reset : in std_logic; -- synchronous, '1' to reset integrator data_enable : in std_logic; -- '1' for clocks carrying new data data : in std_logic_vector; sigma : out std_logic_vector ); end;

---------------- architecture RTL of integrator is begin process(clock) is variable sum: signed(sigma'range); begin if rising_edge(clock) then if reset = '1' then sum := (others => '0'); elsif data_enable = '1' then sum := sum + signed(data); end if; sigma

Reply to
Jonathan Bromley

For that to be a time integrator wouldn't you need to multiply your sigma result with the period of the clock. Of course, this approximates the wave as a series of rectangles of width T. You could do something more complex by drawing a line between two consecutive samples and use that line to make two rectangle with width T/2 opposed to the larger rectangle. Or you could get really fancy and do polynomial interpolation to build finer grain estimates.

---Matthew Hicks

Reply to
Matthew Hicks

Yes, definitely. Sorry, I was cheating and being careless. If the clock enable is asserted once per N clocks (constant N) and the clock period is constant, then the multiplier is constant too; that's my excuse :-)

All perfectly true, as you know much better than I. Perhaps it's time for the OP to give us a bit more information about the application! I'm guessing that the proposed integrator forms part of a feedback loop, so that the sum value definitely won't grow without limit; but that's only a guess... maybe we need the thing to saturate as well. So many questions, so few answers :-)

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Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Jonathan Bromley

Matthew Hicks wrote: (top posting fixed)

-- VHDL code snipped --

Fancier integrator approximations only make sense if delay isn't an issue -- if the application really is agnostic to delay and sensitive to error then the OP should get a book on differential equations that includes a numerical analysis chapter.

If this is going to work in a closed-loop feedback system it's exactly appropriate, and the time scaling will come out in the wash when the integration gain is chosen. If it's going into a demodulator in a communications system, or something like that, then it's more than good enough; any degradation due to 'imperfect' integration will be washed away by signal noise.

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Tim Wescott
Wescott Design Services
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Tim Wescott

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