Hi, I am having a problem with simulation of EDIF netlist file. I have generated EDIF file using leonardospectrum synthesis tool, then created a Xilinx project with ISE and provided the ucf file. But here, I am not able to get the sdf and timesim files for the timing simulation. Please, tell me how to go about this.
netgen can generate a verilog and sdf file from post-par ncd file.
Petter
-- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing?
It's part of the ISE package.
Petter
-- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing?
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